Modifiers
^^^^^^^^^^^^^^^
-TGSI supports modifiers on inputs (as well as saturate modifier on instructions).
+TGSI supports modifiers on inputs (as well as saturate and precise modifier
+on instructions).
+
+For arithmetic instruction having a precise modifier certain optimizations
+which may alter the result are disallowed. Example: *add(mul(a,b),c)* can't be
+optimized to TGSI_OPCODE_MAD, because some hardware only supports the fused
+MAD instruction.
For inputs which have a floating point type, both absolute value and
negation modifiers are supported (with absolute value being applied
.. opcode:: MAD - Multiply And Add
+Perform a * b + c. The implementation is free to decide whether there is an
+intermediate rounding step or not.
+
.. math::
dst.x = src0.x \times src1.x + src2.x
dst.w = src0.w \times src1.w + src2.w
-.. opcode:: DP2A - 2-component Dot Product And Add
-
-.. math::
-
- dst.x = src0.x \times src1.x + src0.y \times src1.y + src2.x
-
- dst.y = src0.x \times src1.x + src0.y \times src1.y + src2.x
-
- dst.z = src0.x \times src1.x + src0.y \times src1.y + src2.x
-
- dst.w = src0.x \times src1.x + src0.y \times src1.y + src2.x
-
-
.. opcode:: FRC - Fraction
.. math::
dst = src0.x^{src1.x}
-.. opcode:: XPD - Cross Product
-
-.. math::
-
- dst.x = src0.y \times src1.z - src1.y \times src0.z
-
- dst.y = src0.z \times src1.x - src1.z \times src0.x
- dst.z = src0.x \times src1.y - src1.x \times src0.y
+.. opcode:: LDEXP - Multiply Number by Integral Power of 2
- dst.w = 1
-
-
-.. opcode:: DPH - Homogeneous Dot Product
-
-This instruction replicates its result.
+src1 is an integer.
.. math::
- dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z + src1.w
+ dst.x = src0.x * 2^{src1.x}
+ dst.y = src0.y * 2^{src1.y}
+ dst.z = src0.z * 2^{src1.z}
+ dst.w = src0.w * 2^{src1.w}
.. opcode:: COS - Cosine
.. opcode:: PK2US - Pack Two Unsigned 16-bit Scalars
- TBD
+This instruction replicates its result.
+
+.. math::
+
+ dst = f32\_to\_unorm16(src.x) | f32\_to\_unorm16(src.y) << 16
.. opcode:: PK4B - Pack Four Signed 8-bit Scalars
- TBD
+This instruction replicates its result.
+
+.. math::
+
+ dst = f32\_to\_snorm8(src.x) |
+ (f32\_to\_snorm8(src.y) << 8) |
+ (f32\_to\_snorm8(src.z) << 16) |
+ (f32\_to\_snorm8(src.w) << 24)
.. opcode:: PK4UB - Pack Four Unsigned 8-bit Scalars
- TBD
+This instruction replicates its result.
+
+.. math::
+
+ dst = f32\_to\_unorm8(src.x) |
+ (f32\_to\_unorm8(src.y) << 8) |
+ (f32\_to\_unorm8(src.z) << 16) |
+ (f32\_to\_unorm8(src.w) << 24)
.. opcode:: SEQ - Set On Equal
Unconditional discard. Allowed in fragment shaders only.
-.. opcode:: SCS - Sine Cosine
-
-.. math::
-
- dst.x = \cos{src.x}
-
- dst.y = \sin{src.x}
-
- dst.z = 0
-
- dst.w = 1
-
-
.. opcode:: TXB - Texture Lookup With Bias
for cube map array textures and shadow cube maps, the bias value
dst = texture\_sample(unit, coord, lod)
-.. opcode:: PUSHA - Push Address Register On Stack
-
- push(src.x)
- push(src.y)
- push(src.z)
- push(src.w)
-
-.. note::
-
- Considered for cleanup.
-
-.. note::
-
- Considered for removal.
-
-.. opcode:: POPA - Pop Address Register From Stack
-
- dst.w = pop()
- dst.z = pop()
- dst.y = pop()
- dst.x = pop()
-
-.. note::
-
- Considered for cleanup.
-
-.. note::
-
- Considered for removal.
-
-
-.. opcode:: CALLNZ - Subroutine Call If Not Zero
-
- TBD
-
-.. note::
-
- Considered for cleanup.
-
-.. note::
-
- Considered for removal.
-
-
Compute ISA
^^^^^^^^^^^^^^^^^^^^^^^^
destination register, which is assumed to be an address (ADDR) register.
-.. opcode:: SAD - Sum Of Absolute Differences
-
-.. math::
-
- dst.x = |src0.x - src1.x| + src2.x
-
- dst.y = |src0.y - src1.y| + src2.y
-
- dst.z = |src0.z - src1.z| + src2.z
-
- dst.w = |src0.w - src1.w| + src2.w
-
-
.. opcode:: TXF - Texel Fetch
As per NV_gpu_shader4, extract a single texel from a specified texture
- image. The source sampler may not be a CUBE or SHADOW. src 0 is a
+ image or PIPE_BUFFER resource. The source sampler may not be a CUBE or
+ SHADOW. src 0 is a
four-component signed integer vector used to identify the single texel
- accessed. 3 components + level. Just like texture instructions, an optional
+ accessed. 3 components + level. If the texture is multisampled, then
+ the fourth component indicates the sample, not the mipmap level.
+ Just like texture instructions, an optional
offset vector is provided, which is subject to various driver restrictions
(regarding range, source of offsets). This instruction ignores the sampler
state.
TXF(uint_vec coord, int_vec offset).
-.. opcode:: TXF_LZ - Texel Fetch
-
- This is the same as TXF with level = 0. Like TXF, it obeys
- pipe_sampler_view::u.tex.first_level.
-
-
.. opcode:: TXQ - Texture Size Query
As per NV_gpu_program4, retrieve the dimensions of the texture depending on
These opcodes are part of :term:`GLSL`'s opcode set. Support for these
opcodes is determined by a special capability bit, ``GLSL``.
-Some require glsl version 1.30 (UIF/BREAKC/SWITCH/CASE/DEFAULT/ENDSWITCH).
+Some require glsl version 1.30 (UIF/SWITCH/CASE/DEFAULT/ENDSWITCH).
.. opcode:: CAL - Subroutine Call
or switch/endswitch.
-.. opcode:: BREAKC - Break Conditional
-
- Conditionally moves the point of execution to the instruction after the
- next endloop or endswitch. The instruction must appear within a loop/endloop
- or switch/endswitch.
- Condition evaluates to true if src0.x != 0 where src0.x is interpreted
- as an integer register.
-
-.. note::
-
- Considered for removal as it's quite inconsistent wrt other opcodes
- (could emulate with UIF/BRK/ENDIF).
-
-
.. opcode:: IF - Float If
Start an IF ... ELSE .. ENDIF block. Condition evaluates to true if
dst.z = src0.zw == src1.zw ? \sim 0 : 0
-.. opcode:: DSNE - Set on Equal
+.. opcode:: DSNE - Set on Not Equal
.. math::
Like the ``frexp()`` routine in many math libraries, this opcode stores the
exponent of its source to ``dst0``, and the significand to ``dst1``, such that
-:math:`dst1 \times 2^{dst0} = src` .
+:math:`dst1 \times 2^{dst0} = src` . The results are replicated across
+channels.
.. math::
- dst0.xy = exp(src.xy)
+ dst0.xy = dst.zw = frac(src.xy)
- dst1.xy = frac(src.xy)
+ dst1 = frac(src.xy)
- dst0.zw = exp(src.zw)
-
- dst1.zw = frac(src.zw)
.. opcode:: DLDEXP - Multiply Number by Integral Power of 2
dst.xy = src0.xy \times 2^{src1.x}
- dst.zw = src0.zw \times 2^{src1.y}
+ dst.zw = src0.zw \times 2^{src1.z}
.. opcode:: DMIN - Minimum
.. math::
- dst.xy = (uint64_t) src0.x
+ dst.xy = (int64_t) src0.x
- dst.zw = (uint64_t) src0.y
+ dst.zw = (int64_t) src0.y
.. opcode:: I2I64 - Signed Integer to 64-bit Integer
NOTE: no driver has implemented this opcode yet (and no state tracker
emits it). This information is subject to change.
+.. opcode:: LOD - level of detail
+
+ Same syntax as the SAMPLE opcode but instead of performing an actual
+ texture lookup/filter, return the computed LOD information that the
+ texture pipe would use to access the texture. The Y component contains
+ the computed LOD lambda_prime. The X component contains the LOD that will
+ be accessed, based on min/max lod's and mipmap filters.
+ The Z and W components are set to 0.
+
+ Syntax: ``LOD dst, address, sampler_view, sampler``
+
+
.. _resourceopcodes:
Resource Access Opcodes
barrier in between.
-.. _threadsyncopcodes:
+.. _bindlessopcodes:
-Inter-thread synchronization opcodes
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Bindless Opcodes
+^^^^^^^^^^^^^^^^
-These opcodes are intended for communication between threads running
-within the same compute grid. For now they're only valid in compute
-programs.
-
-.. opcode:: MFENCE - Memory fence
-
- Syntax: ``MFENCE resource``
+These opcodes are for working with bindless sampler or image handles and
+require PIPE_CAP_BINDLESS_TEXTURE.
- Example: ``MFENCE RES[0]``
+.. opcode:: IMG2HND - Get a bindless handle for a image
- This opcode forces strong ordering between any memory access
- operations that affect the specified resource. This means that
- previous loads and stores (and only those) will be performed and
- visible to other threads before the program execution continues.
+ Syntax: ``IMG2HND dst, image``
+ Example: ``IMG2HND TEMP[0], IMAGE[0]``
-.. opcode:: LFENCE - Load memory fence
+ Sets 'dst' to a bindless handle for 'image'.
- Syntax: ``LFENCE resource``
+.. opcode:: SAMP2HND - Get a bindless handle for a sampler
- Example: ``LFENCE RES[0]``
+ Syntax: ``SAMP2HND dst, sampler``
- Similar to MFENCE, but it only affects the ordering of memory loads.
+ Example: ``SAMP2HND TEMP[0], SAMP[0]``
+ Sets 'dst' to a bindless handle for 'sampler'.
-.. opcode:: SFENCE - Store memory fence
- Syntax: ``SFENCE resource``
-
- Example: ``SFENCE RES[0]``
+.. _threadsyncopcodes:
- Similar to MFENCE, but it only affects the ordering of memory stores.
+Inter-thread synchronization opcodes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+These opcodes are intended for communication between threads running
+within the same compute grid. For now they're only valid in compute
+programs.
.. opcode:: BARRIER - Thread group barrier
concurrent memory access operation that affects the same memory
location is guaranteed to be performed strictly before or after the
entire execution of the atomic operation. The resource may be a BUFFER,
-IMAGE, or MEMORY. In the case of an image, the offset works the same as for
-``LOAD`` and ``STORE``, specified above. These atomic operations may
-only be used with 32-bit integer image formats.
+IMAGE, HWATOMIC, or MEMORY. In the case of an image, the offset works
+the same as for ``LOAD`` and ``STORE``, specified above. For atomic
+counters, the offset is an immediate index to the base hw atomic
+counter for this operation.
+These atomic operations may only be used with 32-bit integer image formats.
.. opcode:: ATOMUADD - Atomic integer addition
resource[offset] = dst_x + src_x
+.. opcode:: ATOMFADD - Atomic floating point addition
+
+ Syntax: ``ATOMFADD dst, resource, offset, src``
+
+ Example: ``ATOMFADD TEMP[0], BUFFER[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically:
+
+.. math::
+
+ dst_x = resource[offset]
+
+ resource[offset] = dst_x + src_x
+
+
.. opcode:: ATOMXCHG - Atomic exchange
Syntax: ``ATOMXCHG dst, resource, offset, src``
resource[offset] = (dst_x > src_x ? dst_x : src_x)
+.. opcode:: ATOMINC_WRAP - Atomic increment + wrap around
+
+ Syntax: ``ATOMINC_WRAP dst, resource, offset, src``
+
+ Example: ``ATOMINC_WRAP TEMP[0], BUFFER[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically:
+
+.. math::
+
+ dst_x = resource[offset] + 1
+
+ resource[offset] = dst_x <= src_x ? dst_x : 0
+
+
+.. opcode:: ATOMDEC_WRAP - Atomic decrement + wrap around
+
+ Syntax: ``ATOMDEC_WRAP dst, resource, offset, src``
+
+ Example: ``ATOMDEC_WRAP TEMP[0], BUFFER[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically:
+
+.. math::
+
+ dst_x = resource[offset]
+
+ resource[offset] = (dst_x > 0 && dst_x < src_x) ? dst_x - 1 : 0
+
+
.. _interlaneopcodes:
Inter-lane opcodes
last vertex processing stage is used.
-TGSI_SEMANTIC_CULLDIST
-""""""""""""""""""""""
-
-Used as distance to plane for performing application-defined culling
-of individual primitives against a plane. When components of vertex
-elements are given this label, these values are assumed to be a
-float32 signed distance to a plane. Primitives will be completely
-discarded if the plane distance for all of the vertices in the
-primitive are < 0. If a vertex has a cull distance of NaN, that
-vertex counts as "out" (as if its < 0);
-The limits on both clip and cull distances are bound
-by the PIPE_MAX_CLIP_OR_CULL_DISTANCE_COUNT define which defines
-the maximum number of components that can be used to hold the
-distances and by the PIPE_MAX_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT
-which specifies the maximum number of registers which can be
-annotated with those semantics.
-
-
TGSI_SEMANTIC_CLIPDIST
""""""""""""""""""""""
Only the X component is used. If per-sample shading is not enabled,
the result is (0, undef, undef, undef).
+Note that if the fragment shader uses this system value, the fragment
+shader is automatically executed at per sample frequency.
+
TGSI_SEMANTIC_SAMPLEPOS
"""""""""""""""""""""""
is in effect. Position values are in the range [0, 1] where 0.5 is
the center of the fragment.
+Note that if the fragment shader uses this system value, the fragment
+shader is automatically executed at per sample frequency.
+
TGSI_SEMANTIC_SAMPLEMASK
""""""""""""""""""""""""
TGSI_SEMANTIC_SUBGROUP_LT_MASK
""""""""""""""""""""""""""""""
-A bit mask of ``bit index > TGSI_SEMANTIC_SUBGROUP_INVOCATION``, i.e.
+A bit mask of ``bit index < TGSI_SEMANTIC_SUBGROUP_INVOCATION``, i.e.
``(1 << subgroup_invocation) - 1`` in arbitrary precision arithmetic.
+TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL
+""""""""""""""""""""""""""""""""""""""
+
+A system value equal to the default_outer_level array set via set_tess_level.
+
+
+TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL
+""""""""""""""""""""""""""""""""""""""
+
+A system value equal to the default_inner_level array set via set_tess_level.
+
+
Declaration Interpolate
^^^^^^^^^^^^^^^^^^^^^^^
Usage of the STORE opcode is only allowed if the WR (writable) flag
is set.
+Hardware Atomic Register File
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Hardware atomics are declared as a 2D array with an optional array id.
+
+The first member of the dimension is the buffer resource the atomic
+is located in.
+The second member is a range into the buffer resource, either for
+one or multiple counters. If this is an array, the declaration will have
+an unique array id.
+
+Each counter is 4 bytes in size, and index and ranges are in counters not bytes.
+DCL HWATOMIC[0][0]
+DCL HWATOMIC[0][1]
+
+This declares two atomics, one at the start of the buffer and one in the
+second 4 bytes.
+
+DCL HWATOMIC[0][0]
+DCL HWATOMIC[1][0]
+DCL HWATOMIC[1][1..3], ARRAY(1)
+
+This declares 5 atomics, one in buffer 0 at 0,
+one in buffer 1 at 0, and an array of 3 atomics in
+the buffer 1, starting at 1.
Properties
^^^^^^^^^^^^^^^^^^^^^^^^
should be set the same way for an entire pipeline. Note that this
applies not only to the literal MUL TGSI opcode, but all FP32
multiplications implied by other operations, such as MAD, FMA, DP2,
-DP3, DP4, DPH, DST, LOG, LRP, XPD, and possibly others. If there is a
+DP3, DP4, DST, LOG, LRP, and possibly others. If there is a
mismatch between shaders, then it is unspecified whether this behavior
will be enabled.
projects / mesa.git / blobdiff