#include "state_tracker/drm_driver.h"
+#define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
+#define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
+
static const struct debug_named_value debug_options[] = {
{"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"},
{"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"},
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
return 1;
+ case PIPE_CAP_NATIVE_FENCE_FD:
+ return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
/* Memory */
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
NON_POWER_OF_TWO); */
+ case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_PRIMITIVE_RESTART:
return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
/* Unsupported features. */
case PIPE_CAP_SEAMLESS_CUBE_MAP:
- case PIPE_CAP_TEXTURE_SWIZZLE: /* XXX supported on gc2000 */
case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_USER_VERTEX_BUFFERS:
- case PIPE_CAP_USER_INDEX_BUFFERS:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
- case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
case PIPE_CAP_DOUBLES:
case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
+ case PIPE_CAP_TGSI_TEX_TXF_LZ:
+ case PIPE_CAP_TGSI_CLOCK:
+ case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+ case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
+ case PIPE_CAP_TGSI_BALLOT:
+ case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
+ case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
+ case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+ case PIPE_CAP_POST_DEPTH_COVERAGE:
+ case PIPE_CAP_BINDLESS_TEXTURE:
return 0;
/* Stream output. */
static float
etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
{
+ struct etna_screen *screen = etna_screen(pscreen);
+
switch (param) {
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
- return 16.0f;
+ return util_last_bit(screen->specs.max_texture_size);
case PIPE_CAPF_GUARD_BAND_LEFT:
case PIPE_CAPF_GUARD_BAND_TOP:
case PIPE_CAPF_GUARD_BAND_RIGHT:
}
static int
-etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
+etna_screen_get_shader_param(struct pipe_screen *pscreen,
+ enum pipe_shader_type shader,
enum pipe_shader_cap param)
{
struct etna_screen *screen = etna_screen(pscreen);
return 64; /* Max native temporaries. */
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return 1;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0; /* nothing uses this */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+ case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
}
}
static bool
-gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt)
+gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
+ enum pipe_format format)
{
+ bool supported = true;
+
if (fmt == TEXTURE_FORMAT_ETC1)
- return VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
+ supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
- return VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
+ supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
+
+ if (fmt & EXT_FORMAT)
+ supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
+
+ if (!supported)
+ return false;
+
+ if (texture_format_needs_swiz(format))
+ return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
return true;
}
return FALSE;
if (usage & PIPE_BIND_RENDER_TARGET) {
- /* If render target, must be RS-supported format that is not rb swapped.
- * Exposing rb swapped (or other swizzled) formats for rendering would
- * involve swizzing in the pixel shader.
- */
- if (translate_rs_format(format) != ETNA_NO_MATCH && !translate_rs_format_rb_swap(format)) {
+ /* if render target, must be RS-supported format */
+ if (translate_rs_format(format) != ETNA_NO_MATCH) {
/* Validate MSAA; number of samples must be allowed, and render target
* must have MSAA'able format. */
if (sample_count > 1) {
if (usage & PIPE_BIND_SAMPLER_VIEW) {
uint32_t fmt = translate_texture_format(format);
- if (!gpu_supports_texure_format(screen, fmt))
+ if (!gpu_supports_texure_format(screen, fmt, format))
fmt = ETNA_NO_MATCH;
if (sample_count < 2 && fmt != ETNA_NO_MATCH)
DBG("could not get ETNA_GPU_PIXEL_PIPES");
goto fail;
}
- if (val < 1 && val > ETNA_MAX_PIXELPIPES) {
- if (val == 0) {
- fprintf(stderr, "Warning: zero pixel pipes (update kernel?)\n");
- val = 1;
- } else {
- fprintf(stderr, "Error: bad pixel pipes value %u\n",
- (unsigned int)val);
- goto fail;
- }
- }
screen->specs.pixel_pipes = val;
if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
screen->model >= 0x1000 || screen->model == 0x880;
screen->specs.npot_tex_any_wrap =
VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
- screen->specs.has_new_sin_cos =
+ screen->specs.has_new_transcendentals =
VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
- if (instruction_count > 256) { /* unified instruction memory? */
+ if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
+ /* GC3000 - this core is capable of loading shaders from
+ * memory. It can also run shaders from registers, as a fallback, but
+ * "max_instructions" does not have the correct value. It has place for
+ * 2*256 instructions just like GC2000, but the offsets are slightly
+ * different.
+ */
screen->specs.vs_offset = 0xC000;
- screen->specs.ps_offset = 0xD000; /* like vivante driver */
+ /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
+ * this mirror for writing PS instructions, probably safest to do the
+ * same.
+ */
+ screen->specs.ps_offset = 0x8000 + 0x1000;
screen->specs.max_instructions = 256;
} else {
- screen->specs.vs_offset = 0x4000;
- screen->specs.ps_offset = 0x6000;
- screen->specs.max_instructions = instruction_count / 2;
+ if (instruction_count > 256) { /* unified instruction memory? */
+ screen->specs.vs_offset = 0xC000;
+ screen->specs.ps_offset = 0xD000; /* like vivante driver */
+ screen->specs.max_instructions = 256;
+ } else {
+ screen->specs.vs_offset = 0x4000;
+ screen->specs.ps_offset = 0x6000;
+ screen->specs.max_instructions = instruction_count / 2;
+ }
}
if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
screen->specs.max_rendertarget_size =
VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
+ screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
+ if (screen->specs.single_buffer)
+ DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
+
return true;
fail:
{
struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
struct pipe_screen *pscreen;
+ drmVersionPtr version;
uint64_t val;
if (!screen)
screen->dev = dev;
screen->gpu = gpu;
screen->ro = renderonly_dup(ro);
+ screen->refcnt = 1;
if (!screen->ro) {
DBG("could not create renderonly object");
goto fail;
}
+ version = drmGetVersion(screen->ro->gpu_fd);
+ screen->drm_version = ETNA_DRM_VERSION(version->version_major,
+ version->version_minor);
+ drmFreeVersion(version);
+
etna_mesa_debug = debug_get_option_etna_mesa_debug();
- /* FIXME: Disable tile status for stability at the moment */
- etna_mesa_debug |= ETNA_DBG_NO_TS;
+ /* Disable autodisable for correct rendering with TS */
+ etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
if (!screen->pipe) {
}
screen->features[4] = val;
+ if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
+ DBG("could not get ETNA_GPU_FEATURES_5");
+ goto fail;
+ }
+ screen->features[5] = val;
+
+ if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
+ DBG("could not get ETNA_GPU_FEATURES_6");
+ goto fail;
+ }
+ screen->features[6] = val;
+
if (!etna_get_specs(screen))
goto fail;
+ /* apply debug options that disable individual features */
+ if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
+ screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
+ if (DBG_ENABLED(ETNA_DBG_NO_TS))
+ screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
+ if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
+ screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
+ if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
+ screen->specs.can_supertile = 0;
+
pscreen->destroy = etna_screen_destroy;
pscreen->get_param = etna_screen_get_param;
pscreen->get_paramf = etna_screen_get_paramf;
projects / mesa.git / blobdiff