#include "etnaviv_resource.h"
#include "etnaviv_translate.h"
-#include "os/os_time.h"
+#include "util/os_time.h"
#include "util/u_math.h"
#include "util/u_memory.h"
+#include "util/u_screen.h"
#include "util/u_string.h"
#include "state_tracker/drm_driver.h"
#define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
#define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
+#define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2)
static const struct debug_named_value debug_options[] = {
{"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"},
{"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
{"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
{"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"},
- {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
+ {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
{"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"},
{"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"},
{"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
{"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"},
{"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
{"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"},
+ {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
DEBUG_NAMED_VALUE_END
};
{
struct etna_screen *screen = etna_screen(pscreen);
+ if (screen->perfmon)
+ etna_perfmon_del(screen->perfmon);
+
if (screen->pipe)
etna_pipe_del(screen->pipe);
switch (param) {
/* Supported features (boolean caps). */
- case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
- case PIPE_CAP_TEXTURE_SHADOW_MAP:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_USER_CONSTANT_BUFFERS:
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
+ case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
return 1;
case PIPE_CAP_NATIVE_FENCE_FD:
return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return 4; /* XXX could easily be supported */
case PIPE_CAP_GLSL_FEATURE_LEVEL:
+ case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
return 120;
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: /* only mirrored repeat */
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
+ case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
- case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
case PIPE_CAP_BINDLESS_TEXTURE:
case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
case PIPE_CAP_QUERY_SO_OVERFLOW:
+ case PIPE_CAP_MEMOBJ:
+ case PIPE_CAP_LOAD_CONSTBUF:
+ case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+ case PIPE_CAP_TILE_RASTER_ORDER:
+ case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+ case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
+ case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
+ case PIPE_CAP_CONTEXT_PRIORITY_MASK:
+ case PIPE_CAP_FENCE_SIGNAL:
+ case PIPE_CAP_CONSTBUF0_FLAGS:
+ case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
+ case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
+ case PIPE_CAP_PACKED_UNIFORMS:
+ case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
+ case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
return 0;
+ case PIPE_CAP_MAX_GS_INVOCATIONS:
+ return 32;
+
+ case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
+ return 1 << 27;
+
/* Stream output. */
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 128;
+ case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
+ return 255;
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
/* Timer queries. */
case PIPE_CAP_QUERY_TIME_ELAPSED:
- case PIPE_CAP_OCCLUSION_QUERY:
return 0;
+ case PIPE_CAP_OCCLUSION_QUERY:
+ return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
case PIPE_CAP_QUERY_TIMESTAMP:
return 1;
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
return 0;
case PIPE_CAP_UMA:
return 1;
+ default:
+ return u_pipe_screen_get_param_defaults(pscreen, param);
}
-
- debug_printf("unknown param %d", param);
- return 0;
}
static float
return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
return util_last_bit(screen->specs.max_texture_size);
- case PIPE_CAPF_GUARD_BAND_LEFT:
- case PIPE_CAPF_GUARD_BAND_TOP:
- case PIPE_CAPF_GUARD_BAND_RIGHT:
- case PIPE_CAPF_GUARD_BAND_BOTTOM:
+ case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
+ case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
+ case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
return 0.0f;
}
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
case PIPE_SHADER_CAP_INTEGERS:
+ case PIPE_SHADER_CAP_INT64_ATOMICS:
+ case PIPE_SHADER_CAP_FP16:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 4096;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+ case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return false;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+ case PIPE_SHADER_CAP_SCALAR_ISA:
return 0;
}
if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
+ if (util_format_is_srgb(format))
+ supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
+
if (fmt & EXT_FORMAT) {
supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
}
+ if (fmt & ASTC_FORMAT) {
+ supported = screen->specs.tex_astc;
+ }
+
if (!supported)
return false;
etna_screen_is_format_supported(struct pipe_screen *pscreen,
enum pipe_format format,
enum pipe_texture_target target,
- unsigned sample_count, unsigned usage)
+ unsigned sample_count,
+ unsigned storage_sample_count,
+ unsigned usage)
{
struct etna_screen *screen = etna_screen(pscreen);
unsigned allowed = 0;
target != PIPE_TEXTURE_RECT)
return FALSE;
+ if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
+ return false;
+
if (usage & PIPE_BIND_RENDER_TARGET) {
/* if render target, must be RS-supported format */
if (translate_rs_format(format) != ETNA_NO_MATCH) {
if (modifiers)
modifiers[num_modifiers] = supported_modifiers[i];
if (external_only)
- external_only[num_modifiers] = 0;
+ external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0;
num_modifiers++;
}
}
screen->specs.num_constants = val;
+ /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
+ * description of the differences. */
+ if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
+ screen->specs.halti = 5; /* New GC7000/GC8x00 */
+ else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
+ screen->specs.halti = 4; /* Old GC7000/GC7400 */
+ else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
+ screen->specs.halti = 3; /* None? */
+ else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
+ screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
+ else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
+ screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
+ else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
+ screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
+ else
+ screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
+ if (screen->specs.halti >= 0)
+ DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti);
+ else
+ DBG("etnaviv: GPU arch: pre-HALTI");
+
screen->specs.can_supertile =
VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
screen->specs.bits_per_tile =
VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
screen->specs.has_new_transcendentals =
VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
-
- if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
+ screen->specs.has_halti2_instructions =
+ VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
+
+ if (screen->specs.halti >= 5) {
+ /* GC7000 - this core must load shaders from memory. */
+ screen->specs.vs_offset = 0;
+ screen->specs.ps_offset = 0;
+ screen->specs.max_instructions = 0; /* Do not program shaders manually */
+ screen->specs.has_icache = true;
+ } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
/* GC3000 - this core is capable of loading shaders from
* memory. It can also run shaders from registers, as a fallback, but
* "max_instructions" does not have the correct value. It has place for
* same.
*/
screen->specs.ps_offset = 0x8000 + 0x1000;
- screen->specs.max_instructions = 256;
+ screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
+ screen->specs.has_icache = true;
} else {
if (instruction_count > 256) { /* unified instruction memory? */
screen->specs.vs_offset = 0xC000;
screen->specs.ps_offset = 0x6000;
screen->specs.max_instructions = instruction_count / 2;
}
+ screen->specs.has_icache = false;
}
if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
screen->specs.max_ps_uniforms = 256;
}
+ if (screen->specs.halti >= 5) {
+ screen->specs.has_unified_uniforms = true;
+ screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
+ screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
+ } else if (screen->specs.halti >= 1) {
+ /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
+ */
+ screen->specs.has_unified_uniforms = true;
+ screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
+ /* hardcode PS uniforms to start after end of VS uniforms -
+ * for more flexibility this offset could be variable based on the
+ * shader.
+ */
+ screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
+ } else {
+ screen->specs.has_unified_uniforms = false;
+ screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
+ screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
+ }
+
screen->specs.max_texture_size =
VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
screen->specs.max_rendertarget_size =
screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
if (screen->specs.single_buffer)
- DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
+ DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
+
+ screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
+
+ screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
return true;
struct etna_screen *screen = etna_screen(pscreen);
struct etna_bo *bo;
- if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
+ if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
bo = etna_bo_from_name(screen->dev, whandle->handle);
- } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
+ } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
} else {
DBG("Attempt to import unsupported handle type %d", whandle->type);
screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
screen->specs.can_supertile = 0;
+ if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
+ screen->specs.single_buffer = 0;
pscreen->destroy = etna_screen_destroy;
pscreen->get_param = etna_screen_get_param;
etna_query_screen_init(pscreen);
etna_resource_screen_init(pscreen);
+ util_dynarray_init(&screen->supported_pm_queries, NULL);
slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
+ if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
+ etna_pm_query_setup(screen);
+
return pscreen;
fail:
projects / mesa.git / blobdiff