etnaviv: keep track of buffer valid ranges for PIPE_BUFFER
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_transfer.c
index 62b876f2d995826d279701d1648341c686f19ed9..77a9abafa99dd7900d026af7a77e4c6b040bcdda 100644 (file)
@@ -174,6 +174,14 @@ etna_transfer_unmap(struct pipe_context *pctx, struct pipe_transfer *ptrans)
    if (!trans->rsc && !(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED))
       etna_bo_cpu_fini(rsc->bo);
 
+   if ((ptrans->resource->target == PIPE_BUFFER) &&
+       (ptrans->usage & PIPE_TRANSFER_WRITE)) {
+      util_range_add(&rsc->base,
+                     &rsc->valid_buffer_range,
+                     ptrans->box.x,
+                     ptrans->box.x + ptrans->box.width);
+      }
+
    pipe_resource_reference(&trans->rsc, NULL);
    pipe_resource_reference(&ptrans->resource, NULL);
    slab_free(&ctx->transfer_pool, trans);
@@ -199,6 +207,17 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc,
    /* slab_alloc() doesn't zero */
    memset(trans, 0, sizeof(*trans));
 
+   /*
+    * Upgrade to UNSYNCHRONIZED if target is PIPE_BUFFER and range is uninitialized.
+    */
+   if ((usage & PIPE_TRANSFER_WRITE) &&
+       (prsc->target == PIPE_BUFFER) &&
+       !util_ranges_intersect(&rsc->valid_buffer_range,
+                              box->x,
+                              box->x + box->width)) {
+      usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
+   }
+
    /* Upgrade DISCARD_RANGE to WHOLE_RESOURCE if the whole resource is
     * being mapped. If we add buffer reallocation to avoid CPU/GPU sync this
     * check needs to be extended to coherent mappings and shared resources.
@@ -460,10 +479,16 @@ fail_prep:
 
 static void
 etna_transfer_flush_region(struct pipe_context *pctx,
-                           struct pipe_transfer *transfer,
+                           struct pipe_transfer *ptrans,
                            const struct pipe_box *box)
 {
-   /* NOOP for now */
+   struct etna_resource *rsc = etna_resource(ptrans->resource);
+
+   if (ptrans->resource->target == PIPE_BUFFER)
+      util_range_add(&rsc->base,
+                     &rsc->valid_buffer_range,
+                     ptrans->box.x + box->x,
+                     ptrans->box.x + box->x + box->width);
 }
 
 void