-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
/*
* Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
*
*/
if (rsc->stencil) {
rsc = rsc->stencil;
- pformat = rsc->base.b.format;
+ pformat = rsc->base.format;
if (bases)
bases++;
}
use_hw_binning(struct fd_batch *batch)
{
struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
- struct pipe_framebuffer_state *pfb = &batch->framebuffer;
- /* this seems to be a hw bug.. but this hack fixes piglit fbo-maxsize: */
- if ((pfb->width > 4096) && (pfb->height > 4096))
+ if ((gmem->maxpw * gmem->maxph) > 32)
+ return false;
+
+ if ((gmem->maxpw > 15) || (gmem->maxph > 15))
return false;
return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
struct fd_resource_slice *slice;
uint32_t offset;
+ if (!rsc->valid)
+ return;
+
if (stencil) {
debug_assert(rsc->stencil);
rsc = rsc->stencil;
- pformat = rsc->base.b.format;
+ pformat = rsc->base.format;
}
slice = &rsc->slices[psurf->u.tex.level];
A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
- DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
+ DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX4_SIZE_8_BIT, 0, 0, NULL);
}
static void
fd4_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
- struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_gmem_stateobj *gmem = &ctx->gmem;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd4_emit emit = {
.debug = &ctx->debug,
- .vtx = &fd4_ctx->solid_vbuf_state,
+ .vtx = &ctx->solid_vbuf_state,
.prog = &ctx->solid_prog,
.key = {
.half_precision = true,
OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
- DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
+ DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX4_SIZE_8_BIT, 0, 0, NULL);
}
static void
fd4_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
- struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_gmem_stateobj *gmem = &ctx->gmem;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd4_emit emit = {
.debug = &ctx->debug,
- .vtx = &fd4_ctx->blit_vbuf_state,
+ .vtx = &ctx->blit_vbuf_state,
.sprite_coord_enable = 1,
/* NOTE: They all use the same VP, this is for vtx bufs. */
.prog = &ctx->blit_prog[0],
y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
OUT_PKT3(ring, CP_MEM_WRITE, 5);
- OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
+ OUT_RELOCW(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
OUT_RING(ring, fui(x0));
OUT_RING(ring, fui(y0));
OUT_RING(ring, fui(x1));
if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
- emit.fp = NULL; /* frag shader changed so clear cache */
+ emit.fs = NULL; /* frag shader changed so clear cache */
fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
}
emit.key.half_precision = true;
break;
}
- emit.fp = NULL; /* frag shader changed so clear cache */
+ emit.fs = NULL; /* frag shader changed so clear cache */
fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
}
struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
*patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
}
- util_dynarray_resize(&batch->draw_patches, 0);
+ util_dynarray_clear(&batch->draw_patches);
}
/* for rendering directly to system memory: */
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
for (i = 0; i < 8; i++) {
- struct fd_vsc_pipe *pipe = &ctx->pipe[i];
+ struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
for (i = 0; i < 8; i++) {
- struct fd_vsc_pipe *pipe = &ctx->pipe[i];
+ struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
if (!pipe->bo) {
pipe->bo = fd_bo_new(ctx->dev, 0x40000,
- DRM_FREEDRENO_GEM_TYPE_KMEM);
+ DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
}
OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
}
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
for (i = 0; i < 8; i++) {
- struct fd_vsc_pipe *pipe = &ctx->pipe[i];
+ struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
}
}
}
/* emit IB to binning drawcmds: */
- ctx->emit_ib(ring, batch->binning);
+ fd4_emit_ib(ring, batch->binning);
- fd_reset_wfi(ctx);
- fd_wfi(ctx, ring);
+ fd_reset_wfi(batch);
+ fd_wfi(batch, ring);
/* and then put stuff back the way it was: */
A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
- fd_event_write(ctx, ring, CACHE_FLUSH);
- fd_wfi(ctx, ring);
+ fd_event_write(batch, ring, CACHE_FLUSH);
+ fd_wfi(batch, ring);
}
/* before first tile */
fd4_emit_tile_init(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
fd4_emit_restore(batch, ring);
update_vsc_pipe(batch);
+ fd_wfi(batch, ring);
+ OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
+ OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
+ A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
+
if (use_hw_binning(batch)) {
OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
} else {
OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
}
-
- if (ctx->needs_rb_fbd) {
- fd_wfi(ctx, ring);
- OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
- OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
- A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
- ctx->needs_rb_fbd = false;
- }
}
/* before IB to rendering cmds: */
uint32_t y2 = tile->yoff + tile->bin_h - 1;
if (use_hw_binning(batch)) {
- struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
+ struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
- assert(pipe->w * pipe->h);
+ assert(pipe->w && pipe->h);
- fd_event_write(ctx, ring, HLSQ_FLUSH);
- fd_wfi(ctx, ring);
+ fd_event_write(batch, ring, HLSQ_FLUSH);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
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