-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
/*
* Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
*
#include "util/u_string.h"
#include "util/u_memory.h"
#include "util/u_inlines.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
#include "freedreno_program.h"
#include "fd4_texture.h"
#include "fd4_format.h"
-static void
-delete_shader_stateobj(struct fd4_shader_stateobj *so)
-{
- ir3_shader_destroy(so->shader);
- free(so);
-}
-
-static struct fd4_shader_stateobj *
-create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
- enum shader_t type)
-{
- struct fd4_shader_stateobj *so = CALLOC_STRUCT(fd4_shader_stateobj);
- struct ir3_compiler *compiler = fd_context(pctx)->screen->compiler;
- so->shader = ir3_shader_create(compiler, cso, type);
- return so;
-}
-
-static void *
-fd4_fp_state_create(struct pipe_context *pctx,
- const struct pipe_shader_state *cso)
-{
- return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
-}
-
-static void
-fd4_fp_state_delete(struct pipe_context *pctx, void *hwcso)
-{
- struct fd4_shader_stateobj *so = hwcso;
- delete_shader_stateobj(so);
-}
-
-static void *
-fd4_vp_state_create(struct pipe_context *pctx,
- const struct pipe_shader_state *cso)
-{
- return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
-}
-
-static void
-fd4_vp_state_delete(struct pipe_context *pctx, void *hwcso)
-{
- struct fd4_shader_stateobj *so = hwcso;
- delete_shader_stateobj(so);
-}
-
static void
emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
{
const struct ir3_info *si = &so->info;
- enum adreno_state_block sb;
- enum adreno_state_src src;
+ enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
+ enum a4xx_state_src src;
uint32_t i, sz, *bin;
- if (so->type == SHADER_VERTEX) {
- sb = SB_VERT_SHADER;
- } else {
- sb = SB_FRAG_SHADER;
- }
-
if (fd_mesa_debug & FD_DBG_DIRECT) {
sz = si->sizedwords;
- src = SS_DIRECT;
+ src = SS4_DIRECT;
bin = fd_bo_map(so->bo);
} else {
sz = 0;
- src = 2; // enums different on a4xx..
+ src = SS4_INDIRECT;
bin = NULL;
}
- OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
- OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
- CP_LOAD_STATE_0_STATE_SRC(src) |
- CP_LOAD_STATE_0_STATE_BLOCK(sb) |
- CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
+ OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
+ OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
+ CP_LOAD_STATE4_0_STATE_SRC(src) |
+ CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
+ CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
if (bin) {
- OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
- CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
+ OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
+ CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
} else {
- OUT_RELOC(ring, so->bo, 0,
- CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
+ OUT_RELOCD(ring, so->bo, 0,
+ CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
}
+
+ /* for how clever coverity is, it is sometimes rather dull, and
+ * doesn't realize that the only case where bin==NULL, sz==0:
+ */
+ assume(bin || (sz == 0));
+
for (i = 0; i < sz; i++) {
OUT_RING(ring, bin[i]);
}
unsigned i;
s[VS].v = fd4_emit_get_vp(emit);
-
- if (emit->key.binning_pass) {
- /* use dummy stateobj to simplify binning vs non-binning: */
- static const struct ir3_shader_variant binning_fp = {};
- s[FS].v = &binning_fp;
- } else {
- s[FS].v = fd4_emit_get_fp(emit);
- }
+ s[FS].v = fd4_emit_get_fp(emit);
s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
{
struct stage s[MAX_STAGES];
uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
- uint32_t face_regid, coord_regid, zwcoord_regid;
+ uint32_t face_regid, coord_regid, zwcoord_regid, vcoord_regid;
enum a3xx_threadsize fssz;
int constmode;
- int i, j, k;
+ int i, j;
debug_assert(nr <= ARRAY_SIZE(color_regid));
+ if (emit->binning_pass)
+ nr = 0;
+
setup_stages(emit, s);
fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
constmode = 1;
pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
+ if (pos_regid == regid(63, 0)) {
+ /* hw dislikes when there is no position output, which can
+ * happen for transform-feedback vertex shaders. Just tell
+ * the hw to use r0.x, with whatever random value is there:
+ */
+ pos_regid = regid(0, 0);
+ }
posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
if (s[FS].v->color0_mrt) {
color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
}
- /* TODO get these dynamically: */
- face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
- coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
- zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
+ face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
+ coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
+ zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
+ vcoord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
/* we could probably divide this up into things that need to be
* emitted if frag-prog is dirty vs if vert-prog is dirty..
OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
0x3f3f000 | /* XXX */
A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
- OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(s[FS].v->pos_regid) |
+ OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(vcoord_regid) |
0xfcfcfc00);
OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
OUT_RING(ring, 0x140010 | /* XXX */
- COND(emit->key.binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
+ COND(emit->binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
OUT_RING(ring, 0x7f | /* XXX */
A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
- COND(s[VS].v->has_samp, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
+ COND(s[VS].v->num_samp > 0, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
OUT_RING(ring, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(s[FS].v->varying_in));
- for (i = 0, j = -1; (i < 16) && (j < (int)s[FS].v->inputs_count); i++) {
+ struct ir3_shader_linkage l = {0};
+ ir3_link_shaders(&l, s[VS].v, s[FS].v);
+
+ for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
uint32_t reg = 0;
OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
- j = ir3_next_varying(s[FS].v, j);
- if (j < s[FS].v->inputs_count) {
- k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].slot);
- reg |= A4XX_SP_VS_OUT_REG_A_REGID(s[VS].v->outputs[k].regid);
- reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(s[FS].v->inputs[j].compmask);
- }
+ reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
+ reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
+ j++;
- j = ir3_next_varying(s[FS].v, j);
- if (j < s[FS].v->inputs_count) {
- k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].slot);
- reg |= A4XX_SP_VS_OUT_REG_B_REGID(s[VS].v->outputs[k].regid);
- reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(s[FS].v->inputs[j].compmask);
- }
+ reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
+ reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
+ j++;
OUT_RING(ring, reg);
}
- for (i = 0, j = -1; (i < 8) && (j < (int)s[FS].v->inputs_count); i++) {
+ for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
uint32_t reg = 0;
OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
- j = ir3_next_varying(s[FS].v, j);
- if (j < s[FS].v->inputs_count)
- reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(s[FS].v->inputs[j].inloc);
- j = ir3_next_varying(s[FS].v, j);
- if (j < s[FS].v->inputs_count)
- reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(s[FS].v->inputs[j].inloc);
- j = ir3_next_varying(s[FS].v, j);
- if (j < s[FS].v->inputs_count)
- reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(s[FS].v->inputs[j].inloc);
- j = ir3_next_varying(s[FS].v, j);
- if (j < s[FS].v->inputs_count)
- reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(s[FS].v->inputs[j].inloc);
+ reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
+ reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
+ reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
+ reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
OUT_RING(ring, reg);
}
A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
- OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
- OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
-
- OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
- OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
- COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
- A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
- A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
- A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
- A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
- A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
- COND(s[FS].v->has_samp, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
- OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
- 0x80000000 | /* XXX */
- COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
- COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
- COND(s[FS].v->frag_coord, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
-
- OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
- OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
- A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
- if (emit->key.binning_pass)
+ if (emit->binning_pass) {
+ OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
+ OUT_RING(ring, 0x00000000); /* SP_FS_LENGTH_REG */
+
+ OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
+ OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
+ COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
+ A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(0) |
+ A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(0) |
+ A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
+ A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
+ A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE);
+ OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
+ 0x80000000);
+
+ OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
+ OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
+ A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
OUT_RING(ring, 0x00000000);
- else
+ } else {
+ OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
+ OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
+
+ OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
+ OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
+ COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
+ A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
+ A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
+ A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
+ A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
+ A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
+ COND(s[FS].v->num_samp > 0, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
+ OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
+ 0x80000000 | /* XXX */
+ COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
+ COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
+ COND(s[FS].v->frag_coord, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
+
+ OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
+ OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
+ A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
+ }
OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
A4XX_RB_RENDER_CONTROL2_WCOORD));
OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
- OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
+ OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(nr) |
COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
- OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
+ OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(nr) |
COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
- COND(emit->key.half_precision,
+ COND(color_regid[i] & HALF_REG_ID,
A4XX_SP_FS_MRT_REG_HALF_PRECISION));
}
- if (emit->key.binning_pass) {
+ if (emit->binning_pass) {
OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |
0x40000000 | /* XXX */
*/
unsigned compmask = s[FS].v->inputs[j].compmask;
- /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
- * instead.. rather than -8 everywhere else..
- */
- uint32_t inloc = s[FS].v->inputs[j].inloc - 8;
+ uint32_t inloc = s[FS].v->inputs[j].inloc;
- if ((s[FS].v->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
+ if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
(s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
uint32_t loc = inloc;
if (s[VS].instrlen)
emit_shader(ring, s[VS].v);
- if (!emit->key.binning_pass)
+ if (!emit->binning_pass)
if (s[FS].instrlen)
emit_shader(ring, s[FS].v);
}
void
fd4_prog_init(struct pipe_context *pctx)
{
- pctx->create_fs_state = fd4_fp_state_create;
- pctx->delete_fs_state = fd4_fp_state_delete;
-
- pctx->create_vs_state = fd4_vp_state_create;
- pctx->delete_vs_state = fd4_vp_state_delete;
-
+ ir3_prog_init(pctx);
fd_prog_init(pctx);
}
projects / mesa.git / blobdiff