freedreno: Split ir3_const's user buffer and indirect upload APIs.
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
index 62bcfd1ca18b05940abcbc87f523960882cce142..1a1037c3a0ee5616f3a23d9aad15197f2bafad8f 100644 (file)
@@ -46,6 +46,8 @@
 #include "fd5_format.h"
 #include "fd5_zsa.h"
 
+#define emit_const_user fd5_emit_const_user
+#define emit_const_bo fd5_emit_const_bo
 #include "ir3_const.h"
 
 /* regid:          base const register
  * sizedwords:     size of const value buffer
  */
 static void
-fd5_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
-               uint32_t regid, uint32_t offset, uint32_t sizedwords,
-               const uint32_t *dwords, struct pipe_resource *prsc)
+fd5_emit_const_user(struct fd_ringbuffer *ring,
+               const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords,
+               const uint32_t *dwords)
 {
-       uint32_t i, sz;
-       enum a4xx_state_src src;
+       emit_const_asserts(ring, v, regid, sizedwords);
 
-       debug_assert((regid % 4) == 0);
-       debug_assert((sizedwords % 4) == 0);
+       OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sizedwords);
+       OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
+                       CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
+                       CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
+                       CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
+       OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
+                       CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
+       OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
+       for (int i = 0; i < sizedwords; i++)
+               OUT_RING(ring, ((uint32_t *)dwords)[i]);
+}
 
-       if (prsc) {
-               sz = 0;
-               src = SS4_INDIRECT;
-       } else {
-               sz = sizedwords;
-               src = SS4_DIRECT;
-       }
+static void
+fd5_emit_const_bo(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
+               uint32_t regid, uint32_t offset, uint32_t sizedwords, struct fd_bo *bo)
+{
+       emit_const_asserts(ring, v, regid, sizedwords);
 
-       OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
+       OUT_PKT7(ring, CP_LOAD_STATE4, 3);
        OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
-                       CP_LOAD_STATE4_0_STATE_SRC(src) |
-                       CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
+                       CP_LOAD_STATE4_0_STATE_SRC(SS4_INDIRECT) |
+                       CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
                        CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
-       if (prsc) {
-               struct fd_bo *bo = fd_resource(prsc)->bo;
-               OUT_RELOC(ring, bo, offset,
-                               CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
-       } else {
-               OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
-                               CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
-               OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
-               dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
-       }
-       for (i = 0; i < sz; i++) {
-               OUT_RING(ring, dwords[i]);
-       }
+       OUT_RELOC(ring, bo, offset,
+                       CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
 }
 
 static void
@@ -130,18 +127,6 @@ is_stateobj(struct fd_ringbuffer *ring)
        return false;
 }
 
-void
-emit_const(struct fd_ringbuffer *ring,
-               const struct ir3_shader_variant *v, uint32_t dst_offset,
-               uint32_t offset, uint32_t size, const void *user_buffer,
-               struct pipe_resource *buffer)
-{
-       /* TODO inline this */
-       assert(dst_offset + size <= v->constlen * 4);
-       fd5_emit_const(ring, v->type, dst_offset,
-                       offset, size, user_buffer, buffer);
-}
-
 static void
 emit_const_ptrs(struct fd_ringbuffer *ring,
                const struct ir3_shader_variant *v, uint32_t dst_offset,