freedreno/a5xx: set missing bary sysvals
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_program.c
index 8f6ee9a687e4d314b4addc47f41a7b00e819bb2a..7065cfe59c76e74e48ea7e0070e442ea73e7ff34 100644 (file)
@@ -28,7 +28,7 @@
 #include "util/u_string.h"
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 #include "util/bitset.h"
 
 #include "freedreno_program.h"
@@ -68,7 +68,7 @@ fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
                                CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
                OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
        } else {
-               OUT_RELOCD(ring, so->bo, 0,
+               OUT_RELOC(ring, so->bo, 0,
                                CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
        }
 
@@ -232,7 +232,8 @@ setup_stages(struct fd5_emit *emit, struct stage *s)
                if (s[i].v) {
                        s[i].i = &s[i].v->info;
                        /* constlen is in units of 4 * vec4: */
-                       s[i].constlen = align(s[i].v->constlen, 4) / 4;
+                       assert(s[i].v->constlen % 4 == 0);
+                       s[i].constlen = s[i].v->constlen / 4;
                        /* instrlen is already in units of 16 instr.. although
                         * probably we should ditch that and not make the compiler
                         * care about instruction group size of a3xx vs a5xx
@@ -286,7 +287,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
        struct stage s[MAX_STAGES];
        uint32_t pos_regid, psize_regid, color_regid[8];
        uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid, samp_mask_regid;
-       uint32_t vcoord_regid, vertex_regid, instance_regid;
+       uint32_t ij_regid[IJ_COUNT], vertex_regid, instance_regid;
        enum a3xx_threadsize fssz;
        uint8_t psize_loc = ~0;
        int i, j;
@@ -320,7 +321,8 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
        face_regid      = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
        coord_regid     = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
        zwcoord_regid   = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
-       vcoord_regid    = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
+       for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
+               ij_regid[i] = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
 
        /* we could probably divide this up into things that need to be
         * emitted if frag-prog is dirty vs if vert-prog is dirty..
@@ -407,27 +409,20 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
                        A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
                        0x6 | /* XXX seems to be always set? */
                        A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(s[VS].v->branchstack) |
-                       COND(s[VS].v->num_samp > 0, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
+                       COND(s[VS].v->need_pixlod, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
 
        struct ir3_shader_linkage l = {0};
-       ir3_link_shaders(&l, s[VS].v, s[FS].v);
+       ir3_link_shaders(&l, s[VS].v, s[FS].v, true);
 
        if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
                        !emit->binning_pass)
                link_stream_out(&l, s[VS].v);
 
-       BITSET_DECLARE(varbs, 128) = {0};
-       uint32_t *varmask = (uint32_t *)varbs;
-
-       for (i = 0; i < l.cnt; i++)
-               for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
-                       BITSET_SET(varbs, l.var[i].loc + j);
-
        OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
-       OUT_RING(ring, ~varmask[0]);  /* VPC_VAR[0].DISABLE */
-       OUT_RING(ring, ~varmask[1]);  /* VPC_VAR[1].DISABLE */
-       OUT_RING(ring, ~varmask[2]);  /* VPC_VAR[2].DISABLE */
-       OUT_RING(ring, ~varmask[3]);  /* VPC_VAR[3].DISABLE */
+       OUT_RING(ring, ~l.varmask[0]);  /* VPC_VAR[0].DISABLE */
+       OUT_RING(ring, ~l.varmask[1]);  /* VPC_VAR[1].DISABLE */
+       OUT_RING(ring, ~l.varmask[2]);  /* VPC_VAR[2].DISABLE */
+       OUT_RING(ring, ~l.varmask[3]);  /* VPC_VAR[3].DISABLE */
 
        /* a5xx appends pos/psize to end of the linkage map: */
        if (pos_regid != regid(63,0))
@@ -494,7 +489,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
        OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
        OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) |
                        COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
-                       COND(s[FS].v->frag_coord, A5XX_VPC_CNTL_0_VARYING) |
+                       COND(s[FS].v->fragcoord_compmask != 0, A5XX_VPC_CNTL_0_VARYING) |
                        0x10000);    // XXX
 
        fd5_context(ctx)->max_loc = l.max_loc;
@@ -516,22 +511,26 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
        OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
                        A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
                        A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
-                       0xfc000000);               /* XXX */
-       OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
-                       0xfcfcfc00);               /* XXX */
+                       A5XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
+       OUT_RING(ring,
+                       A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
+                       A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
+                       A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
+                       A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
        OUT_RING(ring, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
                        A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
-                       0x0000fcfc);               /* XXX */
+                       A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
+                       A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
 
        OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
        OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
-                       COND(s[FS].v->frag_coord, A5XX_SP_FS_CTRL_REG0_VARYING) |
+                       COND(s[FS].v->fragcoord_compmask != 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
                        0x40006 | /* XXX set pretty much everywhere */
                        A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
                        A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
                        A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
                        A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(s[FS].v->branchstack) |
-                       COND(s[FS].v->num_samp > 0, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
+                       COND(s[FS].v->need_pixlod, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
 
        OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
        OUT_RING(ring, 0x020fffff);        /* XXX */
@@ -542,23 +541,29 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
        OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
        OUT_RING(ring, 0x00000010);        /* XXX */
 
+       /* XXX: missing enable bits for per-sample bary linear centroid and IJ_PERSP_SIZE
+        * (should be identical to a6xx)
+        */
+
        OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
-       OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING) |
-                       COND(s[FS].v->frag_coord, A5XX_GRAS_CNTL_XCOORD |
-                                       A5XX_GRAS_CNTL_YCOORD |
-                                       A5XX_GRAS_CNTL_ZCOORD |
-                                       A5XX_GRAS_CNTL_WCOORD |
-                                       A5XX_GRAS_CNTL_UNK3) |
-                       COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_UNK3));
+       OUT_RING(ring,
+                       CONDREG(ij_regid[IJ_PERSP_PIXEL], A5XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
+                       CONDREG(ij_regid[IJ_PERSP_CENTROID], A5XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
+                       COND(s[FS].v->fragcoord_compmask != 0,
+                                       A5XX_GRAS_CNTL_COORD_MASK(s[FS].v->fragcoord_compmask) |
+                                       A5XX_GRAS_CNTL_SIZE) |
+                       COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_SIZE) |
+                       CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_SIZE));
 
        OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
-       OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) |
-                       COND(s[FS].v->frag_coord, A5XX_RB_RENDER_CONTROL0_XCOORD |
-                                       A5XX_RB_RENDER_CONTROL0_YCOORD |
-                                       A5XX_RB_RENDER_CONTROL0_ZCOORD |
-                                       A5XX_RB_RENDER_CONTROL0_WCOORD |
-                                       A5XX_RB_RENDER_CONTROL0_UNK3) |
-                       COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_UNK3));
+       OUT_RING(ring,
+                       CONDREG(ij_regid[IJ_PERSP_PIXEL], A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
+                       CONDREG(ij_regid[IJ_PERSP_CENTROID], A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
+                       COND(s[FS].v->fragcoord_compmask != 0,
+                                       A5XX_RB_RENDER_CONTROL0_COORD_MASK(s[FS].v->fragcoord_compmask) |
+                                       A5XX_RB_RENDER_CONTROL0_SIZE) |
+                       COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_SIZE) |
+                       CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_RB_RENDER_CONTROL0_SIZE));
        OUT_RING(ring,
                        COND(samp_mask_regid != regid(63, 0),
                                A5XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
@@ -621,40 +626,32 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
                                }
                        }
 
-                       gl_varying_slot slot = s[FS].v->inputs[j].slot;
-
-                       /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
-                       if (slot >= VARYING_SLOT_VAR0) {
-                               unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
-                               /* Replace the .xy coordinates with S/T from the point sprite. Set
-                                * interpolation bits for .zw such that they become .01
+                       bool coord_mode = emit->sprite_coord_mode;
+                       if (ir3_point_sprite(s[FS].v, j, emit->sprite_coord_enable, &coord_mode)) {
+                               /* mask is two 2-bit fields, where:
+                                *   '01' -> S
+                                *   '10' -> T
+                                *   '11' -> 1 - T  (flip mode)
                                 */
-                               if (emit->sprite_coord_enable & texmask) {
-                                       /* mask is two 2-bit fields, where:
-                                        *   '01' -> S
-                                        *   '10' -> T
-                                        *   '11' -> 1 - T  (flip mode)
-                                        */
-                                       unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
-                                       uint32_t loc = inloc;
-                                       if (compmask & 0x1) {
-                                               vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
-                                               loc++;
-                                       }
-                                       if (compmask & 0x2) {
-                                               vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
-                                               loc++;
-                                       }
-                                       if (compmask & 0x4) {
-                                               /* .z <- 0.0f */
-                                               vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
-                                               loc++;
-                                       }
-                                       if (compmask & 0x8) {
-                                               /* .w <- 1.0f */
-                                               vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
-                                               loc++;
-                                       }
+                               unsigned mask = coord_mode ? 0b1101 : 0b1001;
+                               uint32_t loc = inloc;
+                               if (compmask & 0x1) {
+                                       vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
+                                       loc++;
+                               }
+                               if (compmask & 0x2) {
+                                       vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
+                                       loc++;
+                               }
+                               if (compmask & 0x4) {
+                                       /* .z <- 0.0f */
+                                       vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
+                                       loc++;
+                               }
+                               if (compmask & 0x8) {
+                                       /* .w <- 1.0f */
+                                       vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
+                                       loc++;
                                }
                        }
                }