ir3, freedreno: Round up constlen earlier

[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_compute.c

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c
index 27ce7e2a29a70d255afd36f31241f513b3758184..438557600f27d93a6eea9216dd452a399b5dd04b 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c
@@ -81,9 +81,8 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
        OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
        OUT_RING(ring, 0xff);
 
-       unsigned constlen = align(v->constlen, 4);
        OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1);
-       OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
+       OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(v->constlen) |
                        A6XX_HLSQ_CS_CNTL_ENABLED);
 
        OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);