#include "fd6_emit.h"
#include "fd6_texture.h"
#include "fd6_format.h"
+#include "fd6_pack.h"
void
fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
unreachable("");
}
+#ifdef DEBUG
+ /* Name should generally match what you get with MESA_SHADER_CAPTURE_PATH: */
+ const char *name = so->shader->nir->info.name;
+ if (name)
+ fd_emit_string5(ring, name, strlen(name));
+#endif
+
OUT_PKT4(ring, instrlen, 1);
OUT_RING(ring, so->instrlen);
static void
setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
{
- OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
- OUT_RING(ring, 0xff); /* XXX */
-
- if (state->ds)
- debug_assert(state->ds->constlen >= state->bs->constlen);
- else
- debug_assert(state->vs->constlen >= state->bs->constlen);
+ OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(
+ .vs_state = true,
+ .hs_state = true,
+ .ds_state = true,
+ .gs_state = true,
+ .fs_state = true,
+ .cs_state = true,
+ .gfx_ibo = true,
+ .cs_ibo = true,
+ ));
+
+ debug_assert(state->vs->constlen >= state->bs->constlen);
OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
- OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
+ OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) |
A6XX_HLSQ_VS_CNTL_ENABLED);
OUT_RING(ring, COND(state->hs,
A6XX_HLSQ_HS_CNTL_ENABLED |
- A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state->hs->constlen, 4))));
+ A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen)));
OUT_RING(ring, COND(state->ds,
A6XX_HLSQ_DS_CNTL_ENABLED |
- A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state->ds->constlen, 4))));
+ A6XX_HLSQ_DS_CNTL_CONSTLEN(state->ds->constlen)));
OUT_RING(ring, COND(state->gs,
A6XX_HLSQ_GS_CNTL_ENABLED |
- A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state->gs->constlen, 4))));
+ A6XX_HLSQ_GS_CNTL_CONSTLEN(state->gs->constlen)));
OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
- OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
+ OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(state->fs->constlen) |
A6XX_HLSQ_FS_CNTL_ENABLED);
OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
uint32_t hs_invocation_regid;
uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
- uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
+ uint32_t ij_regid[IJ_COUNT];
uint32_t gs_header_regid;
enum a3xx_threadsize fssz;
uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
const struct ir3_shader_variant *gs = state->gs;
const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
- if (binning_pass && state->ds)
- ds = state->bs;
- else if (binning_pass)
- vs = state->bs;
+ /* binning VS is wrong when GS is present, so use nonbinning VS
+ * TODO: compile both binning VS/GS variants correctly
+ */
+ if (binning_pass && state->gs)
+ vs = state->vs;
bool sample_shading = fs->per_samp | key->sample_shading;
face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
zwcoord_regid = next_regid(coord_regid, 2);
- ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
- ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
- ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
- ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
+ for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
+ ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
/* If we have pre-dispatch texture fetches, then ij_pix should not
* be DCE'd, even if not actually used in the shader itself:
*/
if (fs->num_sampler_prefetch > 0) {
- assert(VALIDREG(ij_pix_regid));
+ assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
/* also, it seems like ij_pix is *required* to be r0.x */
- assert(ij_pix_regid == regid(0, 0));
+ assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
}
/* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
OUT_RING(ring, 0);
- OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
- OUT_RING(ring, 0x5);
+ OUT_PKT4(ring, REG_A6XX_SP_MODE_CONTROL, 1);
+ OUT_RING(ring, A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
0xfc000000);
enum a3xx_threadsize vssz;
- uint32_t vsregs;
if (ds || hs) {
vssz = TWO_QUADS;
- vsregs = 0;
} else {
vssz = FOUR_QUADS;
- vsregs = A6XX_SP_VS_CTRL_REG0_MERGEDREGS;
}
OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) |
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
- vsregs |
+ A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vs->info.max_half_reg + 1) |
+ COND(vs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
struct ir3_shader_linkage l = {0};
const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
- ir3_link_shaders(&l, last_shader, fs, true);
+
+ bool do_streamout = (last_shader->shader->stream_output.num_outputs > 0);
+
+ /* If we have streamout, link against the real FS, rather than the
+ * dummy FS used for binning pass state, to ensure the OUTLOC's
+ * match. Depending on whether we end up doing sysmem or gmem,
+ * the actual streamout could happen with either the binning pass
+ * or draw pass program, but the same streamout stateobj is used
+ * in either case:
+ */
+ ir3_link_shaders(&l, last_shader, do_streamout ? state->fs : fs, true);
bool primid_passthru = l.primid_loc != 0xff;
OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
/* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
- if (last_shader->shader->stream_output.num_outputs > 0)
- link_stream_out(&l, last_shader);
+ link_stream_out(&l, last_shader);
if (VALIDREG(layer_regid)) {
layer_loc = l.max_loc;
ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
}
- if (last_shader->shader->stream_output.num_outputs > 0) {
+ /* If we have stream-out, we use the full shader for binning
+ * pass, rather than the optimized binning pass one, so that we
+ * have all the varying outputs available for xfb. So streamout
+ * state should always be derived from the non-binning pass
+ * program:
+ */
+ if (do_streamout && !binning_pass) {
setup_stream_out(state, last_shader, &l);
}
OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
+ A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(hs->info.max_half_reg + 1) |
+ COND(hs->mergedregs, A6XX_SP_HS_CTRL_REG0_MERGEDREGS) |
A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs->branchstack) |
COND(hs->need_pixlod, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE));
OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
OUT_RING(ring, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
+ A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds->info.max_half_reg + 1) |
+ COND(ds->mergedregs, A6XX_SP_DS_CTRL_REG0_MERGEDREGS) |
A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds->branchstack) |
COND(ds->need_pixlod, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE));
OUT_RING(ring, hs_info->tess.tcs_vertices_out);
/* Total attribute slots in HS incoming patch. */
- OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
- OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->shader->output_size / 4);
+ OUT_PKT4(ring, REG_A6XX_PC_HS_INPUT_SIZE, 1);
+ OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->output_size / 4);
OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
- OUT_RING(ring, vs->shader->output_size);
+ OUT_RING(ring, vs->output_size);
shader_info *ds_info = &ds->shader->nir->info;
OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
A6XX_PC_TESS_CNTL_OUTPUT(output));
- /* xxx: Misc tess unknowns: */
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9103, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_DS_CLIP_CNTL, 1);
OUT_RING(ring, 0x00ffff00);
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9106, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_DS_LAYER_CNTL, 1);
OUT_RING(ring, 0x0000ffff);
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809D, 1);
+ OUT_PKT4(ring, REG_A6XX_GRAS_DS_LAYER_CNTL, 1);
OUT_RING(ring, 0x0);
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8002, 1);
+ OUT_PKT4(ring, REG_A6XX_GRAS_DS_CL_CNTL, 1);
OUT_RING(ring, 0x0);
- OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
- OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
- A6XX_VPC_PACK_PSIZELOC(255) |
- A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_VS_PACK_PSIZELOC(255) |
+ A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
- OUT_PKT4(ring, REG_A6XX_VPC_PACK_3, 1);
- OUT_RING(ring, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc) |
- A6XX_VPC_PACK_3_PSIZELOC(psize_loc) |
- A6XX_VPC_PACK_3_STRIDE_IN_VPC(l.max_loc));
+ OUT_PKT4(ring, REG_A6XX_VPC_DS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_DS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_DS_PACK_PSIZELOC(psize_loc) |
+ A6XX_VPC_DS_PACK_STRIDE_IN_VPC(l.max_loc));
OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
- OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l.cnt));
+ OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_OUT(l.cnt));
- OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
- OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l.max_loc) |
+ OUT_PKT4(ring, REG_A6XX_PC_DS_OUT_CNTL, 1);
+ OUT_RING(ring, A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
CONDREG(psize_regid, 0x100));
} else {
OUT_RING(ring, 0);
}
- OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
- OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
+ OUT_PKT4(ring, REG_A6XX_SP_VS_PRIMITIVE_CNTL, 1);
+ OUT_RING(ring, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(l.cnt));
bool enable_varyings = fs->total_in > 0;
A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
A6XX_VPC_CNTL_0_UNKLOC(0xff));
- OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
- OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
- CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE));
+ OUT_PKT4(ring, REG_A6XX_PC_VS_OUT_CNTL, 1);
+ OUT_RING(ring, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
+ CONDREG(psize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE));
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
OUT_RING(ring, 0);
OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
- A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
- OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
- A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
- 0xfc00fc00); /* XXX */
+ A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
+ OUT_RING(ring,
+ A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
+ A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
+ A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
+ A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
- A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
- 0x0000fc00); /* XXX */
+ A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
+ A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
OUT_RING(ring, 0xfc); /* XXX */
OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
0x1000000 |
A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
- A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
+ A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fs->info.max_half_reg + 1) |
+ COND(fs->mergedregs, A6XX_SP_FS_CTRL_REG0_MERGEDREGS) |
A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
OUT_RING(ring, 0); /* XXX */
- OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_LAYER_CNTL, 1);
OUT_RING(ring, 0x0000ffff); /* XXX */
+ bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
+ bool need_size_persamp = false;
+ if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
+ if (sample_shading)
+ need_size_persamp = true;
+ else
+ need_size = true;
+ }
+ if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
+ need_size = true;
+
+ /* XXX: enable bits for linear centroid and linear sample bary */
+
OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
OUT_RING(ring,
- CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
- CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
- CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
- COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
- COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
- COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
- A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
- COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
+ CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
+ CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
+ CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
+ COND(need_size, A6XX_GRAS_CNTL_SIZE) |
+ COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
+ COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
OUT_RING(ring,
- CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
- CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
- CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
+ CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
+ CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
+ CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
+ COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
- COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
- COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
- COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
- A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
- COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
+ COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
+ COND(fs->fragcoord_compmask != 0,
+ A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
OUT_RING(ring,
CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
- CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
+ CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
}
- OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
- OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
- A6XX_VPC_PACK_PSIZELOC(psize_loc) |
- A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_VS_PACK_PSIZELOC(psize_loc) |
+ A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
if (gs) {
OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
+ A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(gs->info.max_half_reg + 1) |
+ COND(gs->mergedregs, A6XX_SP_GS_CTRL_REG0_MERGEDREGS) |
A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
else
fd6_emit_link_map(screen, vs, gs, ring);
- OUT_PKT4(ring, REG_A6XX_VPC_PACK_GS, 1);
- OUT_RING(ring, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc) |
- A6XX_VPC_PACK_GS_PSIZELOC(psize_loc) |
- A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l.max_loc));
+ OUT_PKT4(ring, REG_A6XX_VPC_GS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_GS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_GS_PACK_PSIZELOC(psize_loc) |
+ A6XX_VPC_GS_PACK_STRIDE_IN_VPC(l.max_loc));
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9105, 1);
- OUT_RING(ring, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
+ OUT_PKT4(ring, REG_A6XX_VPC_GS_LAYER_CNTL, 1);
+ OUT_RING(ring, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809C, 1);
- OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
+ OUT_PKT4(ring, REG_A6XX_GRAS_GS_LAYER_CNTL, 1);
+ OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
- OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
- OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l.cnt) |
- A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
+ OUT_PKT4(ring, REG_A6XX_SP_GS_PRIMITIVE_CNTL, 1);
+ OUT_RING(ring, A6XX_SP_GS_PRIMITIVE_CNTL_OUT(l.cnt) |
+ A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
- OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
- OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l.max_loc) |
- CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
- CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
- CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
+ OUT_PKT4(ring, REG_A6XX_PC_GS_OUT_CNTL, 1);
+ OUT_RING(ring, A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
+ CONDREG(psize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) |
+ CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) |
+ CONDREG(primitive_regid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID));
uint32_t output;
switch (gs->shader->nir->info.gs.output_primitive) {
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8003, 1);
+ OUT_PKT4(ring, REG_A6XX_GRAS_GS_CL_CNTL, 1);
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
OUT_RING(ring, 0xff);
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9102, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_GS_CLIP_CNTL, 1);
OUT_RING(ring, 0xffff00);
const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
/* Size of per-primitive alloction in ldlw memory in vec4s. */
uint32_t vec4_size =
gs->shader->nir->info.gs.vertices_in *
- DIV_ROUND_UP(prev->shader->output_size, 4);
+ DIV_ROUND_UP(prev->output_size, 4);
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
- OUT_RING(ring, prev->shader->output_size);
+ OUT_RING(ring, prev->output_size);
} else {
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
OUT_RING(ring, 0);
OUT_RING(ring, 0);
}
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9101, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_CLIP_CNTL, 1);
OUT_RING(ring, 0xffff00);
OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
if (fs->instrlen)
fd6_emit_shader(ring, fs);
- OUT_PKT4(ring, REG_A6XX_PC_PRIMID_CNTL, 1);
- OUT_RING(ring, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
+ OUT_REG(ring, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
uint32_t non_sysval_input_count = 0;
for (uint32_t i = 0; i < vs->inputs_count; i++)
fd6_emit_immediates(screen, fs, ring);
}
+static void emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
+ bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable);
+
static struct fd_ringbuffer *
create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
{
- const struct ir3_shader_variant *fs = state->fs;
struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
- uint32_t vinterp[8] = {0};
- /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
- for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
- /* NOTE: varyings are packed, so if compmask is 0xb
- * then first, third, and fourth component occupy
- * three consecutive varying slots:
- */
- unsigned compmask = fs->inputs[j].compmask;
-
- uint32_t inloc = fs->inputs[j].inloc;
-
- if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
- uint32_t loc = inloc;
-
- for (int i = 0; i < 4; i++) {
- if (compmask & (1 << i)) {
- vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
- loc++;
- }
- }
- }
- }
-
- OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
- for (int i = 0; i < 8; i++)
- OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
-
- OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
- for (int i = 0; i < 8; i++)
- OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
+ emit_interp_state(ring, state->fs, false, false, 0);
return ring;
}
struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
emit->ctx->batch->submit, 18 * 4, FD_RINGBUFFER_STREAMING);
- /* slow-path: */
- struct ir3_shader_variant *fs = state->fs;
- uint32_t vinterp[8], vpsrepl[8];
+ emit_interp_state(ring, state->fs, emit->rasterflat,
+ emit->sprite_coord_mode, emit->sprite_coord_enable);
- memset(vinterp, 0, sizeof(vinterp));
- memset(vpsrepl, 0, sizeof(vpsrepl));
+ return ring;
+ }
+}
+
+static void
+emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
+ bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable)
+{
+ uint32_t vinterp[8], vpsrepl[8];
- for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
+ memset(vinterp, 0, sizeof(vinterp));
+ memset(vpsrepl, 0, sizeof(vpsrepl));
- /* NOTE: varyings are packed, so if compmask is 0xb
- * then first, third, and fourth component occupy
- * three consecutive varying slots:
- */
- unsigned compmask = fs->inputs[j].compmask;
+ for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
- uint32_t inloc = fs->inputs[j].inloc;
+ /* NOTE: varyings are packed, so if compmask is 0xb
+ * then first, third, and fourth component occupy
+ * three consecutive varying slots:
+ */
+ unsigned compmask = fs->inputs[j].compmask;
- if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
- (fs->inputs[j].rasterflat && emit->rasterflat)) {
- uint32_t loc = inloc;
+ uint32_t inloc = fs->inputs[j].inloc;
- for (int i = 0; i < 4; i++) {
- if (compmask & (1 << i)) {
- vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
- loc++;
- }
- }
- }
+ if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
+ (fs->inputs[j].rasterflat && rasterflat)) {
+ uint32_t loc = inloc;
- gl_varying_slot slot = fs->inputs[j].slot;
-
- /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
- if (slot >= VARYING_SLOT_VAR0) {
- unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
- /* Replace the .xy coordinates with S/T from the point sprite. Set
- * interpolation bits for .zw such that they become .01
- */
- if (emit->sprite_coord_enable & texmask) {
- /* mask is two 2-bit fields, where:
- * '01' -> S
- * '10' -> T
- * '11' -> 1 - T (flip mode)
- */
- unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
- uint32_t loc = inloc;
- if (compmask & 0x1) {
- vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
- loc++;
- }
- if (compmask & 0x2) {
- vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
- loc++;
- }
- if (compmask & 0x4) {
- /* .z <- 0.0f */
- vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
- loc++;
- }
- if (compmask & 0x8) {
- /* .w <- 1.0f */
- vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
- loc++;
- }
+ for (int i = 0; i < 4; i++) {
+ if (compmask & (1 << i)) {
+ vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
+ loc++;
}
}
}
- OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
- for (int i = 0; i < 8; i++)
- OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
+ bool coord_mode = sprite_coord_mode;
+ if (ir3_point_sprite(fs, j, sprite_coord_enable, &coord_mode)) {
+ /* mask is two 2-bit fields, where:
+ * '01' -> S
+ * '10' -> T
+ * '11' -> 1 - T (flip mode)
+ */
+ unsigned mask = coord_mode ? 0b1101 : 0b1001;
+ uint32_t loc = inloc;
+ if (compmask & 0x1) {
+ vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
+ loc++;
+ }
+ if (compmask & 0x2) {
+ vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
+ loc++;
+ }
+ if (compmask & 0x4) {
+ /* .z <- 0.0f */
+ vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
+ loc++;
+ }
+ if (compmask & 0x8) {
+ /* .w <- 1.0f */
+ vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
+ loc++;
+ }
+ }
+ }
- OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
- for (int i = 0; i < 8; i++)
- OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
+ OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
+ for (int i = 0; i < 8; i++)
+ OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
- return ring;
- }
+ OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
+ for (int i = 0; i < 8; i++)
+ OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
}
static struct ir3_program_state *
static void *
fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
{
- struct fd_context *ctx = fd_context(pctx);
- struct ir3_compiler *compiler = ctx->screen->compiler;
- struct ir3_shader *shader =
- ir3_shader_create(compiler, cso, &ctx->debug, pctx->screen);
- unsigned packets, size;
-
- /* pre-calculate size required for userconst stateobj: */
- fd6_user_consts_size(&shader->ubo_state, &packets, &size);
-
- /* also account for UBO addresses: */
- packets += 1;
- size += 2 * shader->num_ubos;
-
- unsigned sizedwords = (4 * packets) + size;
- shader->ubo_state.cmdstream_size = sizedwords * 4;
-
- return shader;
+ return ir3_shader_state_create(pctx, cso);
}
static void
fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
{
- struct ir3_shader *so = hwcso;
struct fd_context *ctx = fd_context(pctx);
ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
- ir3_shader_destroy(so);
+ ir3_shader_state_delete(pctx, hwcso);
}
void
projects / mesa.git / blobdiff