freedreno/a6xx: Document the bit for the magic 32bit-uniforms-as-16b mode.

[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 72a47c1f5717b8d40e41ccc90ed2b3ff80cdd136..7d57b2d1b5d120aa7011ba3cc407561901789812 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -39,6 +39,7 @@
 #include "fd6_emit.h"
 #include "fd6_texture.h"
 #include "fd6_format.h"
+#include "fd6_pack.h"
 
 void
 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
@@ -225,8 +226,16 @@ setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_varian
 static void
 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
 {
-       OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
-       OUT_RING(ring, 0xff);        /* XXX */
+       OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(
+                       .vs_state = true,
+                       .hs_state = true,
+                       .ds_state = true,
+                       .gs_state = true,
+                       .fs_state = true,
+                       .cs_state = true,
+                       .gfx_ibo = true,
+                       .cs_ibo = true,
+               ));
 
        debug_assert(state->vs->constlen >= state->bs->constlen);
 
@@ -425,8 +434,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
        OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
        OUT_RING(ring, 0);
 
-       OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
-       OUT_RING(ring, 0x5);
+       OUT_PKT4(ring, REG_A6XX_SP_MODE_CONTROL, 1);
+       OUT_RING(ring, A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
 
        OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
        OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
@@ -556,7 +565,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
                OUT_RING(ring, hs_info->tess.tcs_vertices_out);
 
                /* Total attribute slots in HS incoming patch. */
-               OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
+               OUT_PKT4(ring, REG_A6XX_PC_HS_INPUT_SIZE, 1);
                OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->output_size / 4);
 
                OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
@@ -822,8 +831,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
        if (fs->instrlen)
                fd6_emit_shader(ring, fs);
 
-       OUT_PKT4(ring, REG_A6XX_PC_PRIMID_CNTL, 1);
-       OUT_RING(ring, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
+       OUT_REG(ring, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
 
        uint32_t non_sysval_input_count = 0;
        for (uint32_t i = 0; i < vs->inputs_count; i++)