#include "util/u_string.h"
#include "util/u_memory.h"
#include "util/u_inlines.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
#include "util/bitset.h"
#include "freedreno_program.h"
#include "fd6_program.h"
+#include "fd6_const.h"
#include "fd6_emit.h"
#include "fd6_texture.h"
#include "fd6_format.h"
-
-static struct ir3_shader *
-create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
- gl_shader_stage type)
-{
- struct fd_context *ctx = fd_context(pctx);
- struct ir3_compiler *compiler = ctx->screen->compiler;
- return ir3_shader_create(compiler, cso, type, &ctx->debug);
-}
-
-static void *
-fd6_fp_state_create(struct pipe_context *pctx,
- const struct pipe_shader_state *cso)
-{
- return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
-}
-
-static void
-fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
-{
- struct ir3_shader *so = hwcso;
- struct fd_context *ctx = fd_context(pctx);
- ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
- ir3_shader_destroy(so);
-}
-
-static void *
-fd6_vp_state_create(struct pipe_context *pctx,
- const struct pipe_shader_state *cso)
-{
- return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
-}
-
-static void
-fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
-{
- struct ir3_shader *so = hwcso;
- struct fd_context *ctx = fd_context(pctx);
- ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
- ir3_shader_destroy(so);
-}
+#include "fd6_pack.h"
void
fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
{
- const struct ir3_info *si = &so->info;
enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
- enum a6xx_state_src src;
- uint32_t i, sz, *bin;
- unsigned opcode;
-
- if (fd_mesa_debug & FD_DBG_DIRECT) {
- sz = si->sizedwords;
- src = SS6_DIRECT;
- bin = fd_bo_map(so->bo);
- } else {
- sz = 0;
- src = SS6_INDIRECT;
- bin = NULL;
- }
+
+ uint32_t obj_start;
+ uint32_t instrlen;
switch (so->type) {
case MESA_SHADER_VERTEX:
- opcode = CP_LOAD_STATE6_GEOM;
+ obj_start = REG_A6XX_SP_VS_OBJ_START_LO;
+ instrlen = REG_A6XX_SP_VS_INSTRLEN;
+ break;
+ case MESA_SHADER_TESS_CTRL:
+ obj_start = REG_A6XX_SP_HS_OBJ_START_LO;
+ instrlen = REG_A6XX_SP_HS_INSTRLEN;
+ break;
+ case MESA_SHADER_TESS_EVAL:
+ obj_start = REG_A6XX_SP_DS_OBJ_START_LO;
+ instrlen = REG_A6XX_SP_DS_INSTRLEN;
+ break;
+ case MESA_SHADER_GEOMETRY:
+ obj_start = REG_A6XX_SP_GS_OBJ_START_LO;
+ instrlen = REG_A6XX_SP_GS_INSTRLEN;
break;
case MESA_SHADER_FRAGMENT:
+ obj_start = REG_A6XX_SP_FS_OBJ_START_LO;
+ instrlen = REG_A6XX_SP_FS_INSTRLEN;
+ break;
case MESA_SHADER_COMPUTE:
case MESA_SHADER_KERNEL:
- opcode = CP_LOAD_STATE6_FRAG;
+ obj_start = REG_A6XX_SP_CS_OBJ_START_LO;
+ instrlen = REG_A6XX_SP_CS_INSTRLEN;
break;
- default:
- unreachable("bad shader type");
+ case MESA_SHADER_NONE:
+ unreachable("");
}
- OUT_PKT7(ring, opcode, 3 + sz);
+#ifdef DEBUG
+ /* Name should generally match what you get with MESA_SHADER_CAPTURE_PATH: */
+ const char *name = so->shader->nir->info.name;
+ if (name)
+ fd_emit_string5(ring, name, strlen(name));
+#endif
+
+ OUT_PKT4(ring, instrlen, 1);
+ OUT_RING(ring, so->instrlen);
+
+ OUT_PKT4(ring, obj_start, 2);
+ OUT_RELOC(ring, so->bo, 0, 0, 0);
+
+ OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
- CP_LOAD_STATE6_0_STATE_SRC(src) |
+ CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
- if (bin) {
- OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
- OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
- } else {
- OUT_RELOCD(ring, so->bo, 0, 0, 0);
- }
-
- /* for how clever coverity is, it is sometimes rather dull, and
- * doesn't realize that the only case where bin==NULL, sz==0:
- */
- assume(bin || (sz == 0));
-
- for (i = 0; i < sz; i++) {
- OUT_RING(ring, bin[i]);
- }
+ OUT_RELOC(ring, so->bo, 0, 0, 0);
}
/* Add any missing varyings needed for stream-out. Otherwise varyings not
struct ir3_shader_linkage *l)
{
const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
- struct fd6_streamout_state *tf = &state->tf;
- memset(tf, 0, sizeof(*tf));
+ uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
+ uint32_t prog[256/2];
+ uint32_t prog_count;
+
+ memset(ncomp, 0, sizeof(ncomp));
+ memset(prog, 0, sizeof(prog));
- tf->prog_count = align(l->max_loc, 2) / 2;
+ prog_count = align(l->max_loc, 2) / 2;
- debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
+ debug_assert(prog_count < ARRAY_SIZE(prog));
for (unsigned i = 0; i < strmout->num_outputs; i++) {
const struct ir3_stream_output *out = &strmout->output[i];
unsigned k = out->register_index;
unsigned idx;
- tf->ncomp[out->output_buffer] += out->num_components;
+ ncomp[out->output_buffer] += out->num_components;
/* linkage map sorted by order frag shader wants things, so
* a bit less ideal here..
unsigned off = j + out->dst_offset; /* in dwords */
if (loc & 1) {
- tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
+ prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
A6XX_VPC_SO_PROG_B_OFF(off * 4);
} else {
- tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
+ prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
A6XX_VPC_SO_PROG_A_OFF(off * 4);
}
}
}
- tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
- COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
- COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
- COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
- COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
+ struct fd_ringbuffer *ring = state->streamout_stateobj;
+
+ OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * prog_count));
+ OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
+ OUT_RING(ring, A6XX_VPC_SO_BUF_CNTL_ENABLE |
+ COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
+ COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
+ COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
+ COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
+ OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
+ OUT_RING(ring, ncomp[0]);
+ OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
+ OUT_RING(ring, ncomp[1]);
+ OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
+ OUT_RING(ring, ncomp[2]);
+ OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
+ OUT_RING(ring, ncomp[3]);
+ OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
+ OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
+ for (unsigned i = 0; i < prog_count; i++) {
+ OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
+ OUT_RING(ring, prog[i]);
+ }
}
-struct stage {
- const struct ir3_shader_variant *v;
- const struct ir3_info *i;
- /* const sizes are in units of 4 * vec4 */
- uint8_t constoff;
- uint8_t constlen;
- /* instr sizes are in units of 16 instructions */
- uint8_t instroff;
- uint8_t instrlen;
-};
-
-enum {
- VS = 0,
- FS = 1,
- HS = 2,
- DS = 3,
- GS = 4,
- MAX_STAGES
-};
-
static void
-setup_stages(struct fd6_program_state *state, struct stage *s, bool binning_pass)
+setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
{
- unsigned i;
-
- if (binning_pass) {
- static const struct ir3_shader_variant dummy_fs = {0};
-
- s[VS].v = state->bs;
- s[FS].v = &dummy_fs;
- } else {
- s[VS].v = state->vs;
- s[FS].v = state->fs;
- }
-
- s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
-
- for (i = 0; i < MAX_STAGES; i++) {
- if (s[i].v) {
- s[i].i = &s[i].v->info;
- s[i].constlen = align(s[i].v->constlen, 4);
- /* instrlen is already in units of 16 instr.. although
- * probably we should ditch that and not make the compiler
- * care about instruction group size of a3xx vs a5xx
- */
- s[i].instrlen = s[i].v->instrlen;
- } else {
- s[i].i = NULL;
- s[i].constlen = 0;
- s[i].instrlen = 0;
- }
- }
+ OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(
+ .vs_state = true,
+ .hs_state = true,
+ .ds_state = true,
+ .gs_state = true,
+ .fs_state = true,
+ .cs_state = true,
+ .gfx_ibo = true,
+ .cs_ibo = true,
+ ));
+
+ debug_assert(state->vs->constlen >= state->bs->constlen);
- unsigned constoff = 0;
- for (i = 0; i < MAX_STAGES; i++) {
- s[i].constoff = constoff;
- constoff += s[i].constlen;
- }
+ OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
+ OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) |
+ A6XX_HLSQ_VS_CNTL_ENABLED);
+ OUT_RING(ring, COND(state->hs,
+ A6XX_HLSQ_HS_CNTL_ENABLED |
+ A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen)));
+ OUT_RING(ring, COND(state->ds,
+ A6XX_HLSQ_DS_CNTL_ENABLED |
+ A6XX_HLSQ_DS_CNTL_CONSTLEN(state->ds->constlen)));
+ OUT_RING(ring, COND(state->gs,
+ A6XX_HLSQ_GS_CNTL_ENABLED |
+ A6XX_HLSQ_GS_CNTL_CONSTLEN(state->gs->constlen)));
+ OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
+ OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(state->fs->constlen) |
+ A6XX_HLSQ_FS_CNTL_ENABLED);
+
+ OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
+ OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
+ A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state->vs)) |
+ A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
+ A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
+
+ OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
+ OUT_RING(ring, COND(state->hs,
+ A6XX_SP_HS_CONFIG_ENABLED |
+ A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state->hs)) |
+ A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
+ A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
+
+ OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
+ OUT_RING(ring, COND(state->ds,
+ A6XX_SP_DS_CONFIG_ENABLED |
+ A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state->ds)) |
+ A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
+ A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
+
+ OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
+ OUT_RING(ring, COND(state->gs,
+ A6XX_SP_GS_CONFIG_ENABLED |
+ A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state->gs)) |
+ A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
+ A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
+
+ OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
+ OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
+ A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state->fs)) |
+ A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
+ A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
+
+ OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
+ OUT_RING(ring, ir3_shader_nibo(state->fs));
+}
- s[VS].instroff = 0;
- s[FS].instroff = 64 - s[FS].instrlen;
- s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
+static inline uint32_t
+next_regid(uint32_t reg, uint32_t increment)
+{
+ if (VALIDREG(reg))
+ return reg + increment;
+ else
+ return regid(63,0);
}
static void
-setup_stateobj(struct fd_ringbuffer *ring,
- struct fd6_program_state *state, bool binning_pass)
+setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
+ struct fd6_program_state *state, const struct ir3_shader_key *key,
+ bool binning_pass)
{
- struct stage s[MAX_STAGES];
uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
- uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid, samp_mask_regid;
- uint32_t vcoord_regid, vertex_regid, instance_regid;
+ uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
+ uint32_t smask_in_regid, smask_regid;
+ uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
+ uint32_t hs_invocation_regid;
+ uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
+ uint32_t ij_regid[IJ_COUNT];
+ uint32_t gs_header_regid;
enum a3xx_threadsize fssz;
- uint8_t psize_loc = ~0;
+ uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
int i, j;
- setup_stages(state, s, binning_pass);
+ static const struct ir3_shader_variant dummy_fs = {0};
+ const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
+ const struct ir3_shader_variant *hs = state->hs;
+ const struct ir3_shader_variant *ds = state->ds;
+ const struct ir3_shader_variant *gs = state->gs;
+ const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
+
+ /* binning VS is wrong when GS is present, so use nonbinning VS
+ * TODO: compile both binning VS/GS variants correctly
+ */
+ if (binning_pass && state->gs)
+ vs = state->vs;
+
+ bool sample_shading = fs->per_samp | key->sample_shading;
fssz = FOUR_QUADS;
- pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
- psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
- vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
- instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
+ pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
+ psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
+ vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
+ instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
- if (s[FS].v->color0_mrt) {
+ if (hs) {
+ tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
+ tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
+ hs_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
+ ds_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
+ hs_invocation_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
+
+ pos_regid = ir3_find_output_regid(ds, VARYING_SLOT_POS);
+ psize_regid = ir3_find_output_regid(ds, VARYING_SLOT_PSIZ);
+ } else {
+ tess_coord_x_regid = regid(63, 0);
+ tess_coord_y_regid = regid(63, 0);
+ hs_patch_regid = regid(63, 0);
+ ds_patch_regid = regid(63, 0);
+ hs_invocation_regid = regid(63, 0);
+ }
+
+ if (gs) {
+ gs_header_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
+ primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
+ pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
+ psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
+ layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
+ } else {
+ gs_header_regid = regid(63, 0);
+ primitive_regid = regid(63, 0);
+ layer_regid = regid(63, 0);
+ }
+
+ if (fs->color0_mrt) {
color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
- ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
+ ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
} else {
- color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
- color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
- color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
- color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
- color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
- color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
- color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
- color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
+ color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
+ color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
+ color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
+ color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
+ color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
+ color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
+ color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
+ color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
}
- samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
- samp_mask_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
- face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
- coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
- zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
- vcoord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_VARYING_COORD);
- posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
+ samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
+ smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
+ face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
+ coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
+ zwcoord_regid = next_regid(coord_regid, 2);
+ posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
+ smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
+ for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
+ ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
+
+ /* If we have pre-dispatch texture fetches, then ij_pix should not
+ * be DCE'd, even if not actually used in the shader itself:
+ */
+ if (fs->num_sampler_prefetch > 0) {
+ assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
+ /* also, it seems like ij_pix is *required* to be r0.x */
+ assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
+ }
+
+ /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
+ * end up masking the single sample!!
+ */
+ if (!key->msaa)
+ smask_regid = regid(63, 0);
/* we could probably divide this up into things that need to be
* emitted if frag-prog is dirty vs if vert-prog is dirty..
*/
- OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 2);
- OUT_RING(ring, COND(s[VS].v, A6XX_SP_VS_CONFIG_ENABLED) |
- A6XX_SP_VS_CONFIG_NIBO(s[VS].v->image_mapping.num_ibo) |
- A6XX_SP_VS_CONFIG_NTEX(s[VS].v->num_samp) |
- A6XX_SP_VS_CONFIG_NSAMP(s[VS].v->num_samp)); /* SP_VS_CONFIG */
- OUT_RING(ring, s[VS].instrlen); /* SP_VS_INSTRLEN */
-
- OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
- OUT_RING(ring, 0);
-
- OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 2);
- OUT_RING(ring, COND(s[HS].v, A6XX_SP_HS_CONFIG_ENABLED)); /* SP_HS_CONFIG */
- OUT_RING(ring, s[HS].instrlen); /* SP_HS_INSTRLEN */
-
- OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 2);
- OUT_RING(ring, COND(s[DS].v, A6XX_SP_DS_CONFIG_ENABLED)); /* SP_DS_CONFIG */
- OUT_RING(ring, s[DS].instrlen); /* SP_DS_INSTRLEN */
-
- OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
- OUT_RING(ring, 0);
-
- OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 2);
- OUT_RING(ring, COND(s[GS].v, A6XX_SP_GS_CONFIG_ENABLED)); /* SP_GS_CONFIG */
- OUT_RING(ring, s[GS].instrlen); /* SP_GS_INSTRLEN */
-
- OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
- OUT_RING(ring, 0x7fc0);
+ OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A833, 1);
+ OUT_RING(ring, 0x0);
+
+ OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
+ OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
+ A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
+ 0x7000); // XXX
+ for (int i = 0; i < fs->num_sampler_prefetch; i++) {
+ const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
+ OUT_RING(ring, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
+ A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
+ A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
+ A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
+ A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
+ COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
+ A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
+ }
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
OUT_RING(ring, 0);
- OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
- OUT_RING(ring, 0x5);
-
- OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 2);
- OUT_RING(ring, COND(s[FS].v, A6XX_SP_FS_CONFIG_ENABLED) |
- A6XX_SP_FS_CONFIG_NIBO(s[FS].v->image_mapping.num_ibo) |
- A6XX_SP_FS_CONFIG_NTEX(s[FS].v->num_samp) |
- A6XX_SP_FS_CONFIG_NSAMP(s[FS].v->num_samp)); /* SP_FS_CONFIG */
- OUT_RING(ring, s[FS].instrlen); /* SP_FS_INSTRLEN */
+ OUT_PKT4(ring, REG_A6XX_SP_MODE_CONTROL, 1);
+ OUT_RING(ring, A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
- 0xfcfc0000);
-
- OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
- OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(s[VS].constlen) |
- A6XX_HLSQ_VS_CNTL_ENABLED);
- OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(s[HS].constlen)); /* HLSQ_HS_CONSTLEN */
- OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(s[DS].constlen)); /* HLSQ_DS_CONSTLEN */
- OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(s[GS].constlen)); /* HLSQ_GS_CONSTLEN */
+ A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
+ 0xfc000000);
- OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
- OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(s[FS].constlen) |
- A6XX_HLSQ_FS_CNTL_ENABLED);
+ enum a3xx_threadsize vssz;
+ if (ds || hs) {
+ vssz = TWO_QUADS;
+ } else {
+ vssz = FOUR_QUADS;
+ }
OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
- OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
- A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
- A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
- A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s[VS].v->branchstack) |
- COND(s[VS].v->num_samp > 0, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
+ OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) |
+ A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
+ A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vs->info.max_half_reg + 1) |
+ COND(vs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
+ A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
+ COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
- struct ir3_shader_linkage l = {0};
- ir3_link_shaders(&l, s[VS].v, s[FS].v);
-
- if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass)
- link_stream_out(&l, s[VS].v);
+ fd6_emit_shader(ring, vs);
+ fd6_emit_immediates(screen, vs, ring);
- BITSET_DECLARE(varbs, 128) = {0};
- uint32_t *varmask = (uint32_t *)varbs;
+ struct ir3_shader_linkage l = {0};
+ const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
+ ir3_link_shaders(&l, last_shader, fs, true);
- for (i = 0; i < l.cnt; i++)
- for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
- BITSET_SET(varbs, l.var[i].loc + j);
+ bool primid_passthru = l.primid_loc != 0xff;
OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
- OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
- OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
- OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
- OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
+ OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
+ OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
+ OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
+ OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
+
+ /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
+ if (last_shader->shader->stream_output.num_outputs > 0)
+ link_stream_out(&l, last_shader);
+
+ if (VALIDREG(layer_regid)) {
+ layer_loc = l.max_loc;
+ ir3_link_add(&l, layer_regid, 0x1, l.max_loc);
+ }
- /* a6xx appends pos/psize to end of the linkage map: */
- if (pos_regid != regid(63,0))
+ if (VALIDREG(pos_regid)) {
+ pos_loc = l.max_loc;
ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
+ }
- if (psize_regid != regid(63,0)) {
+ if (VALIDREG(psize_regid)) {
psize_loc = l.max_loc;
ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
}
- if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass) {
- setup_stream_out(state, s[VS].v, &l);
+ if (last_shader->shader->stream_output.num_outputs > 0) {
+ setup_stream_out(state, last_shader, &l);
}
- for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
- uint32_t reg = 0;
+ debug_assert(l.cnt < 32);
+ if (gs)
+ OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
+ else if (ds)
+ OUT_PKT4(ring, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
+ else
+ OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
- OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(i), 1);
+ for (j = 0; j < l.cnt; ) {
+ uint32_t reg = 0;
reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
OUT_RING(ring, reg);
}
- for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
- uint32_t reg = 0;
+ if (gs)
+ OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
+ else if (ds)
+ OUT_PKT4(ring, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
+ else
+ OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
- OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(i), 1);
+ for (j = 0; j < l.cnt; ) {
+ uint32_t reg = 0;
reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
OUT_RING(ring, reg);
}
- OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
- OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
-
- if (s[VS].instrlen)
- fd6_emit_shader(ring, s[VS].v);
+ if (hs) {
+ OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
+ OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
+ A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
+ A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(hs->info.max_half_reg + 1) |
+ COND(hs->mergedregs, A6XX_SP_HS_CTRL_REG0_MERGEDREGS) |
+ A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs->branchstack) |
+ COND(hs->need_pixlod, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE));
+
+ fd6_emit_shader(ring, hs);
+ fd6_emit_immediates(screen, hs, ring);
+ fd6_emit_link_map(screen, vs, hs, ring);
+
+ OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
+ OUT_RING(ring, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
+ A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
+ A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds->info.max_half_reg + 1) |
+ COND(ds->mergedregs, A6XX_SP_DS_CTRL_REG0_MERGEDREGS) |
+ A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds->branchstack) |
+ COND(ds->need_pixlod, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE));
+
+ fd6_emit_shader(ring, ds);
+ fd6_emit_immediates(screen, ds, ring);
+ fd6_emit_link_map(screen, hs, ds, ring);
+
+ shader_info *hs_info = &hs->shader->nir->info;
+ OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
+ OUT_RING(ring, hs_info->tess.tcs_vertices_out);
+
+ /* Total attribute slots in HS incoming patch. */
+ OUT_PKT4(ring, REG_A6XX_PC_HS_INPUT_SIZE, 1);
+ OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->output_size / 4);
+
+ OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
+ OUT_RING(ring, vs->output_size);
+
+ shader_info *ds_info = &ds->shader->nir->info;
+ OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
+ uint32_t output;
+ if (ds_info->tess.point_mode)
+ output = TESS_POINTS;
+ else if (ds_info->tess.primitive_mode == GL_ISOLINES)
+ output = TESS_LINES;
+ else if (ds_info->tess.ccw)
+ output = TESS_CCW_TRIS;
+ else
+ output = TESS_CW_TRIS;
+
+ OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
+ A6XX_PC_TESS_CNTL_OUTPUT(output));
+
+ OUT_PKT4(ring, REG_A6XX_VPC_DS_CLIP_CNTL, 1);
+ OUT_RING(ring, 0x00ffff00);
+
+ OUT_PKT4(ring, REG_A6XX_VPC_DS_LAYER_CNTL, 1);
+ OUT_RING(ring, 0x0000ffff);
+
+ OUT_PKT4(ring, REG_A6XX_GRAS_DS_LAYER_CNTL, 1);
+ OUT_RING(ring, 0x0);
+
+ OUT_PKT4(ring, REG_A6XX_GRAS_DS_CL_CNTL, 1);
+ OUT_RING(ring, 0x0);
+
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_VS_PACK_PSIZELOC(255) |
+ A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
+
+ OUT_PKT4(ring, REG_A6XX_VPC_DS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_DS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_DS_PACK_PSIZELOC(psize_loc) |
+ A6XX_VPC_DS_PACK_STRIDE_IN_VPC(l.max_loc));
+
+ OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
+ OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_OUT(l.cnt));
+
+ OUT_PKT4(ring, REG_A6XX_PC_DS_OUT_CNTL, 1);
+ OUT_RING(ring, A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
+ CONDREG(psize_regid, 0x100));
- // TODO depending on other bits in this reg (if any) set somewhere else?
-#if 0
- OUT_PKT4(ring, REG_A6XX_PC_PRIM_VTX_CNTL, 1);
- OUT_RING(ring, COND(s[VS].v->writes_psize, A6XX_PC_PRIM_VTX_CNTL_PSIZE));
-#endif
+ } else {
+ OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
+ OUT_RING(ring, 0);
+ }
- OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
- OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
+ OUT_PKT4(ring, REG_A6XX_SP_VS_PRIMITIVE_CNTL, 1);
+ OUT_RING(ring, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(l.cnt));
- bool enable_varyings = s[FS].v->total_in > 0;
+ bool enable_varyings = fs->total_in > 0;
OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
- OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s[FS].v->total_in) |
+ OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
- 0xff00ff00);
+ A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
+ A6XX_VPC_CNTL_0_UNKLOC(0xff));
- OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
- OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
- COND(psize_regid != regid(63,0), 0x100));
+ OUT_PKT4(ring, REG_A6XX_PC_VS_OUT_CNTL, 1);
+ OUT_RING(ring, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
+ CONDREG(psize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE));
- if (binning_pass) {
- OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
- OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
- OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
- } else {
- OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
- OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
- }
+ OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
+ OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
OUT_RING(ring, 0x7); /* XXX */
OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
- A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
- 0xfc000000); /* XXX */
- OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
- 0xfcfcfc00); /* XXX */
+ A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
+ A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
+ OUT_RING(ring,
+ A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
+ A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
+ A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
+ A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
- A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
- 0x0000fcfc); /* XXX */
+ A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
+ A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
+ A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
OUT_RING(ring, 0xfc); /* XXX */
OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
- OUT_RING(ring, s[FS].v->total_in > 0 ? 3 : 1);
+ OUT_RING(ring, enable_varyings ? 3 : 1);
OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
- COND(s[FS].v->total_in > 0, A6XX_SP_FS_CTRL_REG0_VARYING) |
- COND(s[FS].v->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
+ COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
0x1000000 |
- A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
- A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
- A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s[FS].v->branchstack) |
- COND(s[FS].v->num_samp > 0, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
+ A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
+ A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fs->info.max_half_reg + 1) |
+ COND(fs->mergedregs, A6XX_SP_FS_CTRL_REG0_MERGEDREGS) |
+ A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
+ COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
OUT_RING(ring, 0); /* XXX */
- OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
- OUT_RING(ring, 0xff); /* XXX */
-
- OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_LAYER_CNTL, 1);
OUT_RING(ring, 0x0000ffff); /* XXX */
-#if 0
- OUT_PKT4(ring, REG_A6XX_SP_SP_CNTL, 1);
- OUT_RING(ring, 0x00000010); /* XXX */
-#endif
+ bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
+ bool need_size_persamp = false;
+ if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
+ if (sample_shading)
+ need_size_persamp = true;
+ else
+ need_size = true;
+ }
+ if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
+ need_size = true;
+
+ /* XXX: enable bits for linear centroid and linear sample bary */
OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
- OUT_RING(ring, COND(enable_varyings, A6XX_GRAS_CNTL_VARYING) |
- COND(s[FS].v->frag_coord,
- A6XX_GRAS_CNTL_UNK3 |
- A6XX_GRAS_CNTL_XCOORD |
- A6XX_GRAS_CNTL_YCOORD |
- A6XX_GRAS_CNTL_ZCOORD |
- A6XX_GRAS_CNTL_WCOORD) |
- COND(s[FS].v->frag_face, A6XX_GRAS_CNTL_UNK3));
+ OUT_RING(ring,
+ CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
+ CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
+ CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
+ COND(need_size, A6XX_GRAS_CNTL_SIZE) |
+ COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
+ COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
- OUT_RING(ring, COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_VARYING |
- A6XX_RB_RENDER_CONTROL0_UNK10) |
- COND(s[FS].v->frag_coord,
- A6XX_RB_RENDER_CONTROL0_UNK3 |
- A6XX_RB_RENDER_CONTROL0_XCOORD |
- A6XX_RB_RENDER_CONTROL0_YCOORD |
- A6XX_RB_RENDER_CONTROL0_ZCOORD |
- A6XX_RB_RENDER_CONTROL0_WCOORD) |
- COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL0_UNK3));
-
- OUT_RING(ring, COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
+ OUT_RING(ring,
+ CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
+ CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
+ CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
+ COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
+ COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
+ COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
+ COND(fs->fragcoord_compmask != 0,
+ A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
+
+ OUT_RING(ring,
+ CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
+ CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
+ CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
+ COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
+
+ OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
+ OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
+
+ OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
+ OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
+
+ OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
+ OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
for (i = 0; i < 8; i++) {
- // TODO we could have a mix of half and full precision outputs,
- // we really need to figure out half-precision from IR3_REG_HALF
OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
- COND(false,
- A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
+ COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
}
- OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
- OUT_RING(ring, A6XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
- A6XX_VPC_PACK_PSIZELOC(psize_loc) |
- A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
-
- if (!binning_pass) {
- /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
- for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
- /* NOTE: varyings are packed, so if compmask is 0xb
- * then first, third, and fourth component occupy
- * three consecutive varying slots:
- */
- unsigned compmask = s[FS].v->inputs[j].compmask;
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_VS_PACK_PSIZELOC(psize_loc) |
+ A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
+
+ if (gs) {
+ OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
+ OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
+ A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
+ A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(gs->info.max_half_reg + 1) |
+ COND(gs->mergedregs, A6XX_SP_GS_CTRL_REG0_MERGEDREGS) |
+ A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
+ COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
+
+ fd6_emit_shader(ring, gs);
+ fd6_emit_immediates(screen, gs, ring);
+ if (ds)
+ fd6_emit_link_map(screen, ds, gs, ring);
+ else
+ fd6_emit_link_map(screen, vs, gs, ring);
+
+ OUT_PKT4(ring, REG_A6XX_VPC_GS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_GS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_GS_PACK_PSIZELOC(psize_loc) |
+ A6XX_VPC_GS_PACK_STRIDE_IN_VPC(l.max_loc));
+
+ OUT_PKT4(ring, REG_A6XX_VPC_GS_LAYER_CNTL, 1);
+ OUT_RING(ring, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
+
+ OUT_PKT4(ring, REG_A6XX_GRAS_GS_LAYER_CNTL, 1);
+ OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
+
+ uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
+
+ OUT_PKT4(ring, REG_A6XX_SP_GS_PRIMITIVE_CNTL, 1);
+ OUT_RING(ring, A6XX_SP_GS_PRIMITIVE_CNTL_OUT(l.cnt) |
+ A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
+
+ OUT_PKT4(ring, REG_A6XX_PC_GS_OUT_CNTL, 1);
+ OUT_RING(ring, A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
+ CONDREG(psize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) |
+ CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) |
+ CONDREG(primitive_regid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID));
+
+ uint32_t output;
+ switch (gs->shader->nir->info.gs.output_primitive) {
+ case GL_POINTS:
+ output = TESS_POINTS;
+ break;
+ case GL_LINE_STRIP:
+ output = TESS_LINES;
+ break;
+ case GL_TRIANGLE_STRIP:
+ output = TESS_CW_TRIS;
+ break;
+ default:
+ unreachable("");
+ }
+ OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
+ OUT_RING(ring,
+ A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs->shader->nir->info.gs.vertices_out - 1) |
+ A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
+ A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
- uint32_t inloc = s[FS].v->inputs[j].inloc;
+ OUT_PKT4(ring, REG_A6XX_GRAS_GS_CL_CNTL, 1);
+ OUT_RING(ring, 0);
- if (s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) {
- uint32_t loc = inloc;
+ OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
+ OUT_RING(ring, 0xff);
- for (i = 0; i < 4; i++) {
- if (compmask & (1 << i)) {
- state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
- loc++;
- }
- }
- }
- }
+ OUT_PKT4(ring, REG_A6XX_VPC_GS_CLIP_CNTL, 1);
+ OUT_RING(ring, 0xffff00);
+
+ const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
+
+ /* Size of per-primitive alloction in ldlw memory in vec4s. */
+ uint32_t vec4_size =
+ gs->shader->nir->info.gs.vertices_in *
+ DIV_ROUND_UP(prev->output_size, 4);
+ OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
+ OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
+
+ OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9B07, 1);
+ OUT_RING(ring, 0);
+
+ OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
+ OUT_RING(ring, prev->output_size);
+ } else {
+ OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
+ OUT_RING(ring, 0);
+ OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
+ OUT_RING(ring, 0);
}
- if (!binning_pass)
- if (s[FS].instrlen)
- fd6_emit_shader(ring, s[FS].v);
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_CLIP_CNTL, 1);
+ OUT_RING(ring, 0xffff00);
+
+ OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
+ OUT_RING(ring, 0);
+
+ if (fs->instrlen)
+ fd6_emit_shader(ring, fs);
+
+ OUT_REG(ring, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
+
+ uint32_t non_sysval_input_count = 0;
+ for (uint32_t i = 0; i < vs->inputs_count; i++)
+ if (!vs->inputs[i].sysval)
+ non_sysval_input_count++;
+
+ OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
+ OUT_RING(ring, A6XX_VFD_CONTROL_0_FETCH_CNT(non_sysval_input_count) |
+ A6XX_VFD_CONTROL_0_DECODE_CNT(non_sysval_input_count));
+
+ OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(0), non_sysval_input_count);
+ for (uint32_t i = 0; i < non_sysval_input_count; i++) {
+ assert(vs->inputs[i].compmask);
+ OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
+ A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid));
+ }
OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
- 0xfcfc0000);
- OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
- OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
+ A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
+ 0xfc000000);
+ OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
+ A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
+ OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
+ A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
+ A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
+ 0xfc);
OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
- OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
- OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
+ OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
+ 0xfc00); /* VFD_CONTROL_5 */
+ OUT_RING(ring,
+ COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
+
+ if (!binning_pass)
+ fd6_emit_immediates(screen, fs, ring);
+}
+
+static void emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
+ bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable);
- bool fragz = s[FS].v->has_kill | s[FS].v->writes_pos;
+static struct fd_ringbuffer *
+create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
+{
+ struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
- OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
- OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
+ emit_interp_state(ring, state->fs, false, false, 0);
- OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
- OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
+ return ring;
}
-/* emits the program state which is not part of the stateobj because of
- * dependency on other gl state (rasterflat or sprite-coord-replacement)
+/* build the program streaming state which is not part of the pre-
+ * baked stateobj because of dependency on other gl state (rasterflat
+ * or sprite-coord-replacement)
*/
-void
-fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
+struct fd_ringbuffer *
+fd6_program_interp_state(struct fd6_emit *emit)
{
const struct fd6_program_state *state = fd6_emit_get_prog(emit);
if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
/* fastpath: */
- OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
- for (int i = 0; i < 8; i++)
- OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
-
- OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
- for (int i = 0; i < 8; i++)
- OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
+ return fd_ringbuffer_ref(state->interp_stateobj);
} else {
- /* slow-path: */
- struct ir3_shader_variant *fs = state->fs;
- uint32_t vinterp[8], vpsrepl[8];
+ struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
+ emit->ctx->batch->submit, 18 * 4, FD_RINGBUFFER_STREAMING);
- memset(vinterp, 0, sizeof(vinterp));
- memset(vpsrepl, 0, sizeof(vpsrepl));
+ emit_interp_state(ring, state->fs, emit->rasterflat,
+ emit->sprite_coord_mode, emit->sprite_coord_enable);
- for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
+ return ring;
+ }
+}
- /* NOTE: varyings are packed, so if compmask is 0xb
- * then first, third, and fourth component occupy
- * three consecutive varying slots:
- */
- unsigned compmask = fs->inputs[j].compmask;
+static void
+emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
+ bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable)
+{
+ uint32_t vinterp[8], vpsrepl[8];
- uint32_t inloc = fs->inputs[j].inloc;
+ memset(vinterp, 0, sizeof(vinterp));
+ memset(vpsrepl, 0, sizeof(vpsrepl));
- if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
- (fs->inputs[j].rasterflat && emit->rasterflat)) {
- uint32_t loc = inloc;
+ for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
- for (int i = 0; i < 4; i++) {
- if (compmask & (1 << i)) {
- vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
- loc++;
- }
+ /* NOTE: varyings are packed, so if compmask is 0xb
+ * then first, third, and fourth component occupy
+ * three consecutive varying slots:
+ */
+ unsigned compmask = fs->inputs[j].compmask;
+
+ uint32_t inloc = fs->inputs[j].inloc;
+
+ if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
+ (fs->inputs[j].rasterflat && rasterflat)) {
+ uint32_t loc = inloc;
+
+ for (int i = 0; i < 4; i++) {
+ if (compmask & (1 << i)) {
+ vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
+ loc++;
}
}
+ }
- gl_varying_slot slot = fs->inputs[j].slot;
-
- /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
- if (slot >= VARYING_SLOT_VAR0) {
- unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
- /* Replace the .xy coordinates with S/T from the point sprite. Set
- * interpolation bits for .zw such that they become .01
- */
- if (emit->sprite_coord_enable & texmask) {
- /* mask is two 2-bit fields, where:
- * '01' -> S
- * '10' -> T
- * '11' -> 1 - T (flip mode)
- */
- unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
- uint32_t loc = inloc;
- if (compmask & 0x1) {
- vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
- loc++;
- }
- if (compmask & 0x2) {
- vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
- loc++;
- }
- if (compmask & 0x4) {
- /* .z <- 0.0f */
- vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
- loc++;
- }
- if (compmask & 0x8) {
- /* .w <- 1.0f */
- vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
- loc++;
- }
- }
+ bool coord_mode = sprite_coord_mode;
+ if (ir3_point_sprite(fs, j, sprite_coord_enable, &coord_mode)) {
+ /* mask is two 2-bit fields, where:
+ * '01' -> S
+ * '10' -> T
+ * '11' -> 1 - T (flip mode)
+ */
+ unsigned mask = coord_mode ? 0b1101 : 0b1001;
+ uint32_t loc = inloc;
+ if (compmask & 0x1) {
+ vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
+ loc++;
+ }
+ if (compmask & 0x2) {
+ vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
+ loc++;
+ }
+ if (compmask & 0x4) {
+ /* .z <- 0.0f */
+ vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
+ loc++;
+ }
+ if (compmask & 0x8) {
+ /* .w <- 1.0f */
+ vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
+ loc++;
}
}
+ }
- OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
- for (int i = 0; i < 8; i++)
- OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
+ OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
+ for (int i = 0; i < 8; i++)
+ OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
- OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
- for (int i = 0; i < 8; i++)
- OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
- }
+ OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
+ for (int i = 0; i < 8; i++)
+ OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
}
static struct ir3_program_state *
fd6_program_create(void *data, struct ir3_shader_variant *bs,
struct ir3_shader_variant *vs,
+ struct ir3_shader_variant *hs,
+ struct ir3_shader_variant *ds,
+ struct ir3_shader_variant *gs,
struct ir3_shader_variant *fs,
const struct ir3_shader_key *key)
{
struct fd_context *ctx = data;
struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
- state->bs = bs;
+ /* if we have streamout, use full VS in binning pass, as the
+ * binning pass VS will have outputs on other than position/psize
+ * stripped out:
+ */
+ state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
state->vs = vs;
+ state->hs = hs;
+ state->ds = ds;
+ state->gs = gs;
state->fs = fs;
+ state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
+ state->streamout_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
+
- setup_stateobj(state->binning_stateobj, state, true);
- setup_stateobj(state->stateobj, state, false);
+#ifdef DEBUG
+ if (!ds) {
+ for (unsigned i = 0; i < bs->inputs_count; i++) {
+ if (vs->inputs[i].sysval)
+ continue;
+ debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
+ }
+ }
+#endif
+
+ setup_config_stateobj(state->config_stateobj, state);
+ setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
+ setup_stateobj(state->stateobj, ctx->screen, state, key, false);
+ state->interp_stateobj = create_interp_stateobj(ctx, state);
return &state->base;
}
struct fd6_program_state *so = fd6_program_state(state);
fd_ringbuffer_del(so->stateobj);
fd_ringbuffer_del(so->binning_stateobj);
+ fd_ringbuffer_del(so->config_stateobj);
+ fd_ringbuffer_del(so->interp_stateobj);
+ fd_ringbuffer_del(so->streamout_stateobj);
free(so);
}
.destroy_state = fd6_program_destroy,
};
+static void *
+fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
+{
+ return ir3_shader_state_create(pctx, cso);
+}
+
+static void
+fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
+{
+ struct fd_context *ctx = fd_context(pctx);
+ ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
+ ir3_shader_state_delete(pctx, hwcso);
+}
+
void
fd6_prog_init(struct pipe_context *pctx)
{
fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
- pctx->create_fs_state = fd6_fp_state_create;
- pctx->delete_fs_state = fd6_fp_state_delete;
+ pctx->create_vs_state = fd6_shader_state_create;
+ pctx->delete_vs_state = fd6_shader_state_delete;
+
+ pctx->create_tcs_state = fd6_shader_state_create;
+ pctx->delete_tcs_state = fd6_shader_state_delete;
+
+ pctx->create_tes_state = fd6_shader_state_create;
+ pctx->delete_tes_state = fd6_shader_state_delete;
+
+ pctx->create_gs_state = fd6_shader_state_create;
+ pctx->delete_gs_state = fd6_shader_state_delete;
+
+ pctx->create_gs_state = fd6_shader_state_create;
+ pctx->delete_gs_state = fd6_shader_state_delete;
- pctx->create_vs_state = fd6_vp_state_create;
- pctx->delete_vs_state = fd6_vp_state_delete;
+ pctx->create_fs_state = fd6_shader_state_create;
+ pctx->delete_fs_state = fd6_shader_state_delete;
fd_prog_init(pctx);
}
projects / mesa.git / blobdiff