#include "a5xx/fd5_screen.h"
#include "a6xx/fd6_screen.h"
+/* for fd_get_driver/device_uuid() */
+#include "common/freedreno_uuid.h"
#include "ir3/ir3_nir.h"
#include "ir3/ir3_compiler.h"
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_INVALIDATE_BUFFER:
case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
+ case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
+ case PIPE_CAP_NIR_COMPACT_ARRAYS:
return 1;
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
return is_a3xx(screen) || is_a4xx(screen);
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
- return is_a5xx(screen) || is_a6xx(screen);
+ return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
if (is_a3xx(screen)) return 16;
return 10;
case PIPE_CAP_UMA:
return 1;
+ case PIPE_CAP_MEMOBJ:
+ return fd_device_version(screen->dev) >= FD_VERSION_MEMORY_FD;
case PIPE_CAP_NATIVE_FENCE_FD:
return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
default:
case PIPE_SHADER_CAP_INTEGERS:
return is_ir3(screen) ? 1 : 0;
case PIPE_SHADER_CAP_INT64_ATOMICS:
- case PIPE_SHADER_CAP_FP16_DERIVATIVES:
- case PIPE_SHADER_CAP_INT16:
+ case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+ case PIPE_SHADER_CAP_INT16:
+ case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
return 0;
case PIPE_SHADER_CAP_FP16:
return ((is_a5xx(screen) || is_a6xx(screen)) &&
fd_fence_ref(ptr, pfence);
}
+static void
+fd_screen_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
+{
+ struct fd_screen *screen = fd_screen(pscreen);
+
+ fd_get_device_uuid(uuid, screen->gpu_id);
+}
+
+static void
+fd_screen_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
+{
+ fd_get_driver_uuid(uuid);
+}
+
struct pipe_screen *
fd_screen_create(struct fd_device *dev, struct renderonly *ro)
{
pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
+ pscreen->get_device_uuid = fd_screen_get_device_uuid;
+ pscreen->get_driver_uuid = fd_screen_get_driver_uuid;
+
slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
return pscreen;