freedreno: Enable GL_EXT_memory_object and GL_EXT_memory_object_fd

[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c

diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 27ad3697798be2dfa0370e9fe80290aee31ad505..9f0867ba83af6119a950515d9f70e9ee984b2d39 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -57,8 +57,11 @@
 #include "a5xx/fd5_screen.h"
 #include "a6xx/fd6_screen.h"
 
+/* for fd_get_driver/device_uuid() */
+#include "common/freedreno_uuid.h"
 
 #include "ir3/ir3_nir.h"
+#include "ir3/ir3_compiler.h"
 #include "a2xx/ir2.h"
 
 static const struct debug_named_value debug_options[] = {
@@ -159,7 +162,9 @@ fd_screen_destroy(struct pipe_screen *pscreen)
 
        simple_mtx_destroy(&screen->lock);
 
-       ralloc_free(screen->compiler);
+       if (screen->compiler)
+               ir3_compiler_destroy(screen->compiler);
+
        ralloc_free(screen->live_batches);
 
        free(screen->perfcntr_queries);
@@ -195,6 +200,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_BARRIER:
        case PIPE_CAP_INVALIDATE_BUFFER:
        case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
+       case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
+       case PIPE_CAP_NIR_COMPACT_ARRAYS:
                return 1;
 
        case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
@@ -232,6 +239,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
        case PIPE_CAP_VERTEX_SHADER_SATURATE:
        case PIPE_CAP_PRIMITIVE_RESTART:
+       case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
        case PIPE_CAP_TGSI_INSTANCEID:
        case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
        case PIPE_CAP_INDEP_BLEND_ENABLE:
@@ -257,7 +265,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                return is_a3xx(screen) || is_a4xx(screen);
 
        case PIPE_CAP_POLYGON_OFFSET_CLAMP:
-               return is_a5xx(screen) || is_a6xx(screen);
+               return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 
        case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
                if (is_a3xx(screen)) return 16;
@@ -389,6 +397,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
        case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
        case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
+       case PIPE_CAP_TGSI_TEXCOORD:
                if (is_ir3(screen))
                        return 1;
                return 0;
@@ -444,6 +453,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                return 10;
        case PIPE_CAP_UMA:
                return 1;
+       case PIPE_CAP_MEMOBJ:
+               return fd_device_version(screen->dev) >= FD_VERSION_MEMORY_FD;
        case PIPE_CAP_NATIVE_FENCE_FD:
                return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
        default:
@@ -565,8 +576,9 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
        case PIPE_SHADER_CAP_INTEGERS:
                return is_ir3(screen) ? 1 : 0;
        case PIPE_SHADER_CAP_INT64_ATOMICS:
-        case PIPE_SHADER_CAP_FP16_DERIVATIVES:
-        case PIPE_SHADER_CAP_INT16:
+       case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+       case PIPE_SHADER_CAP_INT16:
+       case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
                return 0;
        case PIPE_SHADER_CAP_FP16:
                return ((is_a5xx(screen) || is_a6xx(screen)) &&
@@ -711,6 +723,19 @@ fd_get_compiler_options(struct pipe_screen *pscreen,
        return ir2_get_compiler_options();
 }
 
+static struct disk_cache *
+fd_get_disk_shader_cache(struct pipe_screen *pscreen)
+{
+       struct fd_screen *screen = fd_screen(pscreen);
+
+       if (is_ir3(screen)) {
+               struct ir3_compiler *compiler = screen->compiler;
+               return compiler->disk_cache;
+       }
+
+       return NULL;
+}
+
 bool
 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
                struct fd_bo *bo,
@@ -799,6 +824,20 @@ static void _fd_fence_ref(struct pipe_screen *pscreen,
        fd_fence_ref(ptr, pfence);
 }
 
+static void
+fd_screen_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
+{
+       struct fd_screen *screen = fd_screen(pscreen);
+
+       fd_get_device_uuid(uuid, screen->gpu_id);
+}
+
+static void
+fd_screen_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
+{
+       fd_get_driver_uuid(uuid);
+}
+
 struct pipe_screen *
 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 {
@@ -988,6 +1027,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
        pscreen->get_shader_param = fd_screen_get_shader_param;
        pscreen->get_compute_param = fd_get_compute_param;
        pscreen->get_compiler_options = fd_get_compiler_options;
+       pscreen->get_disk_shader_cache = fd_get_disk_shader_cache;
 
        fd_resource_screen_init(pscreen);
        fd_query_screen_init(pscreen);
@@ -1005,6 +1045,9 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 
        pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
 
+       pscreen->get_device_uuid = fd_screen_get_device_uuid;
+       pscreen->get_driver_uuid = fd_screen_get_driver_uuid;
+
        slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 
        return pscreen;