#include "iris_context.h"
#include "nir/tgsi_to_nir.h"
-#define KEY_INIT_NO_ID(gen) \
- .tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
- .tex.compressed_multisample_layout_mask = ~0, \
- .tex.msaa_16 = (gen >= 9 ? ~0 : 0)
-#define KEY_INIT(gen) .program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
+#define KEY_ID(prefix) .prefix.program_string_id = ish->program_id
+#define BRW_KEY_INIT(gen, prog_id) \
+ .base.program_string_id = prog_id, \
+ .base.subgroup_size_type = BRW_SUBGROUP_SIZE_UNIFORM, \
+ .base.tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
+ .base.tex.compressed_multisample_layout_mask = ~0, \
+ .base.tex.msaa_16 = (gen >= 9 ? ~0 : 0)
static unsigned
get_new_program_id(struct iris_screen *screen)
return p_atomic_inc_return(&screen->program_id);
}
+static struct brw_vs_prog_key
+iris_to_brw_vs_key(const struct gen_device_info *devinfo,
+ const struct iris_vs_prog_key *key)
+{
+ return (struct brw_vs_prog_key) {
+ BRW_KEY_INIT(devinfo->gen, key->vue.base.program_string_id),
+
+ /* Don't tell the backend about our clip plane constants, we've
+ * already lowered them in NIR and don't want it doing it again.
+ */
+ .nr_userclip_plane_consts = 0,
+ };
+}
+
+static struct brw_tcs_prog_key
+iris_to_brw_tcs_key(const struct gen_device_info *devinfo,
+ const struct iris_tcs_prog_key *key)
+{
+ return (struct brw_tcs_prog_key) {
+ BRW_KEY_INIT(devinfo->gen, key->vue.base.program_string_id),
+ .tes_primitive_mode = key->tes_primitive_mode,
+ .input_vertices = key->input_vertices,
+ .patch_outputs_written = key->patch_outputs_written,
+ .outputs_written = key->outputs_written,
+ .quads_workaround = key->quads_workaround,
+ };
+}
+
+static struct brw_tes_prog_key
+iris_to_brw_tes_key(const struct gen_device_info *devinfo,
+ const struct iris_tes_prog_key *key)
+{
+ return (struct brw_tes_prog_key) {
+ BRW_KEY_INIT(devinfo->gen, key->vue.base.program_string_id),
+ .patch_inputs_read = key->patch_inputs_read,
+ .inputs_read = key->inputs_read,
+ };
+}
+
+static struct brw_gs_prog_key
+iris_to_brw_gs_key(const struct gen_device_info *devinfo,
+ const struct iris_gs_prog_key *key)
+{
+ return (struct brw_gs_prog_key) {
+ BRW_KEY_INIT(devinfo->gen, key->vue.base.program_string_id),
+ };
+}
+
+static struct brw_wm_prog_key
+iris_to_brw_fs_key(const struct gen_device_info *devinfo,
+ const struct iris_fs_prog_key *key)
+{
+ return (struct brw_wm_prog_key) {
+ BRW_KEY_INIT(devinfo->gen, key->base.program_string_id),
+ .nr_color_regions = key->nr_color_regions,
+ .flat_shade = key->flat_shade,
+ .alpha_test_replicate_alpha = key->alpha_test_replicate_alpha,
+ .alpha_to_coverage = key->alpha_to_coverage,
+ .clamp_fragment_color = key->clamp_fragment_color,
+ .persample_interp = key->persample_interp,
+ .multisample_fbo = key->multisample_fbo,
+ .force_dual_color_blend = key->force_dual_color_blend,
+ .coherent_fb_fetch = key->coherent_fb_fetch,
+ .color_outputs_valid = key->color_outputs_valid,
+ .input_slots_valid = key->input_slots_valid,
+ .ignore_sample_mask_out = !key->multisample_fbo,
+ };
+}
+
+static struct brw_cs_prog_key
+iris_to_brw_cs_key(const struct gen_device_info *devinfo,
+ const struct iris_cs_prog_key *key)
+{
+ return (struct brw_cs_prog_key) {
+ BRW_KEY_INIT(devinfo->gen, key->base.program_string_id),
+ };
+}
+
static void *
upload_state(struct u_upload_mgr *uploader,
struct iris_state_ref *ref,
struct pipe_context *ctx = &ice->ctx;
struct iris_screen *screen = (struct iris_screen *) ctx->screen;
- // XXX: these are not retained forever, use a separate uploader?
void *map =
upload_state(ice->state.surface_uploader, surf_state,
screen->isl_dev.ss.size, 64);
: ISL_FORMAT_R32G32B32A32_FLOAT,
.swizzle = ISL_SWIZZLE_IDENTITY,
.stride_B = 1,
- .mocs = ice->vtbl.mocs(res->bo));
+ .mocs = iris_mocs(res->bo, &screen->isl_dev));
}
static nir_ssa_def *
case nir_intrinsic_image_deref_load:
case nir_intrinsic_image_deref_store:
case nir_intrinsic_image_deref_atomic_add:
- case nir_intrinsic_image_deref_atomic_min:
- case nir_intrinsic_image_deref_atomic_max:
+ case nir_intrinsic_image_deref_atomic_imin:
+ case nir_intrinsic_image_deref_atomic_umin:
+ case nir_intrinsic_image_deref_atomic_imax:
+ case nir_intrinsic_image_deref_atomic_umax:
case nir_intrinsic_image_deref_atomic_and:
case nir_intrinsic_image_deref_atomic_or:
case nir_intrinsic_image_deref_atomic_xor:
}
}
-// XXX: need unify_interfaces() at link time...
+/**
+ * Undo nir_lower_passthrough_edgeflags but keep the inputs_read flag.
+ */
+static bool
+iris_fix_edge_flags(nir_shader *nir)
+{
+ if (nir->info.stage != MESA_SHADER_VERTEX) {
+ nir_shader_preserve_all_metadata(nir);
+ return false;
+ }
+
+ nir_variable *var = NULL;
+ nir_foreach_variable(v, &nir->outputs) {
+ if (v->data.location == VARYING_SLOT_EDGE) {
+ var = v;
+ break;
+ }
+ }
+
+ if (!var) {
+ nir_shader_preserve_all_metadata(nir);
+ return false;
+ }
+
+ exec_node_remove(&var->node);
+ var->data.mode = nir_var_shader_temp;
+ exec_list_push_tail(&nir->globals, &var->node);
+ nir->info.outputs_written &= ~VARYING_BIT_EDGE;
+ nir->info.inputs_read &= ~VERT_BIT_EDGEFLAG;
+ nir_fixup_deref_modes(nir);
+
+ nir_foreach_function(f, nir) {
+ if (f->impl) {
+ nir_metadata_preserve(f->impl, nir_metadata_block_index |
+ nir_metadata_dominance |
+ nir_metadata_live_ssa_defs |
+ nir_metadata_loop_analysis);
+ } else {
+ nir_metadata_preserve(f->impl, nir_metadata_all);
+ }
+ }
+
+ return true;
+}
/**
* Fix an uncompiled shader's stream output info.
{
UNUSED const struct gen_device_info *devinfo = compiler->devinfo;
- /* The intel compiler assumes that num_uniforms is in bytes. For
- * scalar that means 4 bytes per uniform slot.
- *
- * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
- */
- nir->num_uniforms *= 4;
-
const unsigned IRIS_MAX_SYSTEM_VALUES =
PIPE_MAX_SHADER_IMAGES * BRW_IMAGE_PARAM_SIZE;
enum brw_param_builtin *system_values =
unsigned patch_vert_idx = -1;
unsigned ucp_idx[IRIS_MAX_CLIP_PLANES];
unsigned img_idx[PIPE_MAX_SHADER_IMAGES];
+ unsigned variable_group_size_idx = -1;
memset(ucp_idx, -1, sizeof(ucp_idx));
memset(img_idx, -1, sizeof(img_idx));
load_ubo->num_components = intrin->num_components;
load_ubo->src[0] = nir_src_for_ssa(temp_const_ubo_name);
load_ubo->src[1] = nir_src_for_ssa(offset);
+ nir_intrinsic_set_align(load_ubo,
+ nir_intrinsic_align_mul(intrin),
+ nir_intrinsic_align_offset(intrin));
nir_ssa_dest_init(&load_ubo->instr, &load_ubo->dest,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size,
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
nir_variable *var = nir_deref_instr_get_variable(deref);
- /* XXX: var->data.binding is not set properly. We need to run
- * some form of gl_nir_lower_samplers_as_deref() to get it.
- * This breaks tests which use more than one image.
- */
if (img_idx[var->data.binding] == -1) {
/* GL only allows arrays of arrays of images. */
assert(glsl_type_is_image(glsl_without_array(var->type)));
nir_intrinsic_base(intrin) * 16));
break;
}
+ case nir_intrinsic_load_local_group_size: {
+ assert(nir->info.cs.local_size_variable);
+ if (variable_group_size_idx == -1) {
+ variable_group_size_idx = num_system_values;
+ num_system_values += 3;
+ for (int i = 0; i < 3; i++) {
+ system_values[variable_group_size_idx + i] =
+ BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X + i;
+ }
+ }
+
+ b.cursor = nir_before_instr(instr);
+ offset = nir_imm_int(&b, variable_group_size_idx * sizeof(uint32_t));
+ break;
+ }
default:
continue;
}
load->num_components = comps;
load->src[0] = nir_src_for_ssa(temp_ubo_name);
load->src[1] = nir_src_for_ssa(offset);
+ nir_intrinsic_set_align(load, 4, 0);
nir_ssa_dest_init(&load->instr, &load->dest, comps, 32, NULL);
nir_builder_instr_insert(&b, &load->instr);
nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
nir_validate_shader(nir, "before remapping");
- /* Place the new params at the front of constant buffer 0. */
+ /* Uniforms are stored in constant buffer 0, the
+ * user-facing UBOs are indexed by one. So if any constant buffer is
+ * needed, the constant buffer 0 will be needed, so account for it.
+ */
+ unsigned num_cbufs = nir->info.num_ubos;
+ if (num_cbufs || nir->num_uniforms)
+ num_cbufs++;
+
+ /* Place the new params in a new cbuf. */
if (num_system_values > 0) {
- nir->num_uniforms += num_system_values * sizeof(uint32_t);
+ unsigned sysval_cbuf_index = num_cbufs;
+ num_cbufs++;
system_values = reralloc(mem_ctx, system_values, enum brw_param_builtin,
num_system_values);
assert(load->src[0].is_ssa);
if (load->src[0].ssa == temp_ubo_name) {
+ nir_ssa_def *imm = nir_imm_int(&b, sysval_cbuf_index);
nir_instr_rewrite_src(instr, &load->src[0],
- nir_src_for_ssa(nir_imm_int(&b, 0)));
- } else if (nir_src_is_const(load->src[0]) &&
- nir_src_as_uint(load->src[0]) == 0) {
- nir_ssa_def *offset =
- nir_iadd(&b, load->src[1].ssa,
- nir_imm_int(&b, 4 * num_system_values));
- nir_instr_rewrite_src(instr, &load->src[1],
- nir_src_for_ssa(offset));
+ nir_src_for_ssa(imm));
}
}
}
system_values = NULL;
}
+ assert(num_cbufs < PIPE_MAX_CONSTANT_BUFFERS);
nir_validate_shader(nir, "after remap");
- /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
- * about it for compute shaders, so go ahead and make some fake ones
- * which the backend will dead code eliminate.
+ /* We don't use params[] but gallium leaves num_uniforms set. We use this
+ * to detect when cbuf0 exists but we don't need it anymore when we get
+ * here. Instead, zero it out so that the back-end doesn't get confused
+ * when nr_params * 4 != num_uniforms != nr_params * 4.
*/
- prog_data->nr_params = nir->num_uniforms / 4;
- prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
-
- /* System values and uniforms are stored in constant buffer 0, the
- * user-facing UBOs are indexed by one. So if any constant buffer is
- * needed, the constant buffer 0 will be needed, so account for it.
- */
- unsigned num_cbufs = nir->info.num_ubos;
- if (num_cbufs || num_system_values || nir->num_uniforms)
- num_cbufs++;
+ nir->num_uniforms = 0;
/* Constant loads (if any) need to go at the end of the constant buffers so
* we need to know num_cbufs before we can lower to them.
static const char *surface_group_names[] = {
[IRIS_SURFACE_GROUP_RENDER_TARGET] = "render target",
+ [IRIS_SURFACE_GROUP_RENDER_TARGET_READ] = "non-coherent render target read",
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS] = "CS work groups",
[IRIS_SURFACE_GROUP_TEXTURE] = "texture",
[IRIS_SURFACE_GROUP_UBO] = "ubo",
* Set up the binding table indices and apply to the shader.
*/
static void
-iris_setup_binding_table(struct nir_shader *nir,
+iris_setup_binding_table(const struct gen_device_info *devinfo,
+ struct nir_shader *nir,
struct iris_binding_table *bt,
unsigned num_render_targets,
unsigned num_system_values,
/* All render targets used. */
bt->used_mask[IRIS_SURFACE_GROUP_RENDER_TARGET] =
BITFIELD64_MASK(num_render_targets);
+
+ /* Setup render target read surface group inorder to support non-coherent
+ * framebuffer fetch on Gen8
+ */
+ if (devinfo->gen == 8 && info->outputs_read) {
+ bt->sizes[IRIS_SURFACE_GROUP_RENDER_TARGET_READ] = num_render_targets;
+ bt->used_mask[IRIS_SURFACE_GROUP_RENDER_TARGET_READ] =
+ BITFIELD64_MASK(num_render_targets);
+ }
} else if (info->stage == MESA_SHADER_COMPUTE) {
bt->sizes[IRIS_SURFACE_GROUP_CS_WORK_GROUPS] = 1;
- bt->used_mask[IRIS_SURFACE_GROUP_CS_WORK_GROUPS] = 1;
}
bt->sizes[IRIS_SURFACE_GROUP_TEXTURE] = util_last_bit(info->textures_used);
*/
bt->sizes[IRIS_SURFACE_GROUP_UBO] = num_cbufs + 1;
- /* The first IRIS_MAX_ABOs indices in the SSBO group are for atomics, real
- * SSBOs start after that. Compaction will remove unused ABOs.
- */
- bt->sizes[IRIS_SURFACE_GROUP_SSBO] = IRIS_MAX_ABOS + info->num_ssbos;
+ bt->sizes[IRIS_SURFACE_GROUP_SSBO] = info->num_ssbos;
for (int i = 0; i < IRIS_SURFACE_GROUP_COUNT; i++)
assert(bt->sizes[i] <= SURFACE_GROUP_MAX_ELEMENTS);
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
switch (intrin->intrinsic) {
+ case nir_intrinsic_load_num_work_groups:
+ bt->used_mask[IRIS_SURFACE_GROUP_CS_WORK_GROUPS] = 1;
+ break;
+
+ case nir_intrinsic_load_output:
+ if (devinfo->gen == 8) {
+ mark_used_with_src(bt, &intrin->src[0],
+ IRIS_SURFACE_GROUP_RENDER_TARGET_READ);
+ }
+ break;
+
case nir_intrinsic_image_size:
case nir_intrinsic_image_load:
case nir_intrinsic_image_store:
case nir_intrinsic_image_atomic_add:
- case nir_intrinsic_image_atomic_min:
- case nir_intrinsic_image_atomic_max:
+ case nir_intrinsic_image_atomic_imin:
+ case nir_intrinsic_image_atomic_umin:
+ case nir_intrinsic_image_atomic_imax:
+ case nir_intrinsic_image_atomic_umax:
case nir_intrinsic_image_atomic_and:
case nir_intrinsic_image_atomic_or:
case nir_intrinsic_image_atomic_xor:
case nir_intrinsic_image_load:
case nir_intrinsic_image_store:
case nir_intrinsic_image_atomic_add:
- case nir_intrinsic_image_atomic_min:
- case nir_intrinsic_image_atomic_max:
+ case nir_intrinsic_image_atomic_imin:
+ case nir_intrinsic_image_atomic_umin:
+ case nir_intrinsic_image_atomic_imax:
+ case nir_intrinsic_image_atomic_umax:
case nir_intrinsic_image_atomic_and:
case nir_intrinsic_image_atomic_or:
case nir_intrinsic_image_atomic_xor:
IRIS_SURFACE_GROUP_SSBO);
break;
+ case nir_intrinsic_load_output:
+ if (devinfo->gen == 8) {
+ rewrite_src_with_bti(&b, bt, instr, &intrin->src[0],
+ IRIS_SURFACE_GROUP_RENDER_TARGET_READ);
+ }
+ break;
+
case nir_intrinsic_get_buffer_size:
case nir_intrinsic_ssbo_atomic_add:
case nir_intrinsic_ssbo_atomic_imin:
static void
iris_debug_recompile(struct iris_context *ice,
struct shader_info *info,
- unsigned program_string_id,
- const void *key)
+ const struct brw_base_prog_key *key)
{
struct iris_screen *screen = (struct iris_screen *) ice->ctx.screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
const struct brw_compiler *c = screen->compiler;
if (!info)
info->name ? info->name : "(no identifier)",
info->label ? info->label : "");
- const void *old_key =
- iris_find_previous_compile(ice, info->stage, program_string_id);
-
- brw_debug_key_recompile(c, &ice->dbg, info->stage, old_key, key);
+ const void *old_iris_key =
+ iris_find_previous_compile(ice, info->stage, key->program_string_id);
+
+ union brw_any_prog_key old_key;
+
+ switch (info->stage) {
+ case MESA_SHADER_VERTEX:
+ old_key.vs = iris_to_brw_vs_key(devinfo, old_iris_key);
+ break;
+ case MESA_SHADER_TESS_CTRL:
+ old_key.tcs = iris_to_brw_tcs_key(devinfo, old_iris_key);
+ break;
+ case MESA_SHADER_TESS_EVAL:
+ old_key.tes = iris_to_brw_tes_key(devinfo, old_iris_key);
+ break;
+ case MESA_SHADER_GEOMETRY:
+ old_key.gs = iris_to_brw_gs_key(devinfo, old_iris_key);
+ break;
+ case MESA_SHADER_FRAGMENT:
+ old_key.wm = iris_to_brw_fs_key(devinfo, old_iris_key);
+ break;
+ case MESA_SHADER_COMPUTE:
+ old_key.cs = iris_to_brw_cs_key(devinfo, old_iris_key);
+ break;
+ default:
+ unreachable("invalid shader stage");
+ }
+
+ brw_debug_key_recompile(c, &ice->dbg, info->stage, &old_key.base, key);
}
+/**
+ * Get the shader for the last enabled geometry stage.
+ *
+ * This stage is the one which will feed stream output and the rasterizer.
+ */
+static gl_shader_stage
+last_vue_stage(struct iris_context *ice)
+{
+ if (ice->shaders.uncompiled[MESA_SHADER_GEOMETRY])
+ return MESA_SHADER_GEOMETRY;
+
+ if (ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
+ return MESA_SHADER_TESS_EVAL;
+
+ return MESA_SHADER_VERTEX;
+}
/**
* Compile a vertex shader, and upload the assembly.
static struct iris_compiled_shader *
iris_compile_vs(struct iris_context *ice,
struct iris_uncompiled_shader *ish,
- const struct brw_vs_prog_key *key)
+ const struct iris_vs_prog_key *key)
{
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
const struct brw_compiler *compiler = screen->compiler;
nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
- if (key->nr_userclip_plane_consts) {
+ if (key->vue.nr_userclip_plane_consts) {
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
- nir_lower_clip_vs(nir, (1 << key->nr_userclip_plane_consts) - 1, true);
+ nir_lower_clip_vs(nir, (1 << key->vue.nr_userclip_plane_consts) - 1,
+ true, false, NULL);
nir_lower_io_to_temporaries(nir, impl, true, false);
nir_lower_global_vars_to_local(nir);
nir_lower_vars_to_ssa(nir);
&num_system_values, &num_cbufs);
struct iris_binding_table bt;
- iris_setup_binding_table(nir, &bt, /* num_render_targets */ 0,
+ iris_setup_binding_table(devinfo, nir, &bt, /* num_render_targets */ 0,
num_system_values, num_cbufs);
brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
brw_compute_vue_map(devinfo,
&vue_prog_data->vue_map, nir->info.outputs_written,
- nir->info.separate_shader);
+ nir->info.separate_shader, /* pos_slots */ 1);
- /* Don't tell the backend about our clip plane constants, we've already
- * lowered them in NIR and we don't want it doing it again.
- */
- struct brw_vs_prog_key key_no_ucp = *key;
- key_no_ucp.nr_userclip_plane_consts = 0;
+ struct brw_vs_prog_key brw_key = iris_to_brw_vs_key(devinfo, key);
char *error_str = NULL;
const unsigned *program =
- brw_compile_vs(compiler, &ice->dbg, mem_ctx, &key_no_ucp, vs_prog_data,
- nir, -1, &error_str);
+ brw_compile_vs(compiler, &ice->dbg, mem_ctx, &brw_key, vs_prog_data,
+ nir, -1, NULL, &error_str);
if (program == NULL) {
dbg_printf("Failed to compile vertex shader: %s\n", error_str);
ralloc_free(mem_ctx);
}
if (ish->compiled_once) {
- iris_debug_recompile(ice, &nir->info, key->program_string_id, key);
+ iris_debug_recompile(ice, &nir->info, &brw_key.base);
} else {
ish->compiled_once = true;
}
uint32_t *so_decls =
- ice->vtbl.create_so_decl_list(&ish->stream_output,
+ screen->vtbl.create_so_decl_list(&ish->stream_output,
&vue_prog_data->vue_map);
struct iris_compiled_shader *shader =
static void
iris_update_compiled_vs(struct iris_context *ice)
{
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_VERTEX];
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_VERTEX];
- struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_vs_prog_key key = { KEY_INIT(devinfo->gen) };
- ice->vtbl.populate_vs_key(ice, &ish->nir->info, &key);
+ struct iris_vs_prog_key key = { KEY_ID(vue.base) };
+ screen->vtbl.populate_vs_key(ice, &ish->nir->info, last_vue_stage(ice), &key);
struct iris_compiled_shader *old = ice->shaders.prog[IRIS_CACHE_VS];
struct iris_compiled_shader *shader =
if (old != shader) {
ice->shaders.prog[IRIS_CACHE_VS] = shader;
- ice->state.dirty |= IRIS_DIRTY_VS |
- IRIS_DIRTY_BINDINGS_VS |
- IRIS_DIRTY_CONSTANTS_VS |
- IRIS_DIRTY_VF_SGVS;
+ ice->state.dirty |= IRIS_DIRTY_VF_SGVS;
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_VS |
+ IRIS_STAGE_DIRTY_BINDINGS_VS |
+ IRIS_STAGE_DIRTY_CONSTANTS_VS;
+ shs->sysvals_need_upload = true;
+
const struct brw_vs_prog_data *vs_prog_data =
(void *) shader->prog_data;
const bool uses_draw_params = vs_prog_data->uses_firstvertex ||
const bool needs_sgvs_element = uses_draw_params ||
vs_prog_data->uses_instanceid ||
vs_prog_data->uses_vertexid;
- bool needs_edge_flag = false;
- nir_foreach_variable(var, &ish->nir->inputs) {
- if (var->data.location == VERT_ATTRIB_EDGEFLAG)
- needs_edge_flag = true;
- }
if (ice->state.vs_uses_draw_params != uses_draw_params ||
ice->state.vs_uses_derived_draw_params != uses_derived_draw_params ||
- ice->state.vs_needs_edge_flag != needs_edge_flag) {
+ ice->state.vs_needs_edge_flag != ish->needs_edge_flag) {
ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
IRIS_DIRTY_VERTEX_ELEMENTS;
}
ice->state.vs_uses_draw_params = uses_draw_params;
ice->state.vs_uses_derived_draw_params = uses_derived_draw_params;
ice->state.vs_needs_sgvs_element = needs_sgvs_element;
- ice->state.vs_needs_edge_flag = needs_edge_flag;
+ ice->state.vs_needs_edge_flag = ish->needs_edge_flag;
}
}
static struct iris_compiled_shader *
iris_compile_tcs(struct iris_context *ice,
struct iris_uncompiled_shader *ish,
- const struct brw_tcs_prog_key *key)
+ const struct iris_tcs_prog_key *key)
{
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
const struct brw_compiler *compiler = screen->compiler;
rzalloc(mem_ctx, struct brw_tcs_prog_data);
struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
+ const struct gen_device_info *devinfo = &screen->devinfo;
enum brw_param_builtin *system_values = NULL;
unsigned num_system_values = 0;
unsigned num_cbufs = 0;
struct iris_binding_table bt;
+ struct brw_tcs_prog_key brw_key = iris_to_brw_tcs_key(devinfo, key);
+
if (ish) {
nir = nir_shader_clone(mem_ctx, ish->nir);
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
&num_system_values, &num_cbufs);
- iris_setup_binding_table(nir, &bt, /* num_render_targets */ 0,
+ iris_setup_binding_table(devinfo, nir, &bt, /* num_render_targets */ 0,
num_system_values, num_cbufs);
brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
} else {
- nir = brw_nir_create_passthrough_tcs(mem_ctx, compiler, options, key);
+ nir =
+ brw_nir_create_passthrough_tcs(mem_ctx, compiler, options, &brw_key);
/* Reserve space for passing the default tess levels as constants. */
+ num_cbufs = 1;
num_system_values = 8;
system_values =
rzalloc_array(mem_ctx, enum brw_param_builtin, num_system_values);
char *error_str = NULL;
const unsigned *program =
- brw_compile_tcs(compiler, &ice->dbg, mem_ctx, key, tcs_prog_data, nir,
- -1, &error_str);
+ brw_compile_tcs(compiler, &ice->dbg, mem_ctx, &brw_key, tcs_prog_data,
+ nir, -1, NULL, &error_str);
if (program == NULL) {
dbg_printf("Failed to compile control shader: %s\n", error_str);
ralloc_free(mem_ctx);
if (ish) {
if (ish->compiled_once) {
- iris_debug_recompile(ice, &nir->info, key->program_string_id, key);
+ iris_debug_recompile(ice, &nir->info, &brw_key.base);
} else {
ish->compiled_once = true;
}
static void
iris_update_compiled_tcs(struct iris_context *ice)
{
+ struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_TESS_CTRL];
struct iris_uncompiled_shader *tcs =
ice->shaders.uncompiled[MESA_SHADER_TESS_CTRL];
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ const struct brw_compiler *compiler = screen->compiler;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct shader_info *tes_info =
iris_get_shader_info(ice, MESA_SHADER_TESS_EVAL);
- struct brw_tcs_prog_key key = {
- KEY_INIT_NO_ID(devinfo->gen),
- .program_string_id = tcs ? tcs->program_id : 0,
+ struct iris_tcs_prog_key key = {
+ .vue.base.program_string_id = tcs ? tcs->program_id : 0,
.tes_primitive_mode = tes_info->tess.primitive_mode,
- .input_vertices = ice->state.vertices_per_patch,
+ .input_vertices =
+ !tcs || compiler->use_tcs_8_patch ? ice->state.vertices_per_patch : 0,
+ .quads_workaround = devinfo->gen < 9 &&
+ tes_info->tess.primitive_mode == GL_QUADS &&
+ tes_info->tess.spacing == TESS_SPACING_EQUAL,
};
get_unified_tess_slots(ice, &key.outputs_written,
&key.patch_outputs_written);
- ice->vtbl.populate_tcs_key(ice, &key);
+ screen->vtbl.populate_tcs_key(ice, &key);
struct iris_compiled_shader *old = ice->shaders.prog[IRIS_CACHE_TCS];
struct iris_compiled_shader *shader =
if (old != shader) {
ice->shaders.prog[IRIS_CACHE_TCS] = shader;
- ice->state.dirty |= IRIS_DIRTY_TCS |
- IRIS_DIRTY_BINDINGS_TCS |
- IRIS_DIRTY_CONSTANTS_TCS;
-
- if (!tcs) {
- /* We're binding a passthrough TCS, which doesn't have uniforms.
- * Since there's no actual TCS, the state tracker doesn't bother
- * to call set_constant_buffers to clear stale constant buffers.
- *
- * We do upload TCS constants for the default tesslevel system
- * values, however. In this case, we would see stale constant
- * data and try and read a dangling cbuf0->user_buffer pointer.
- * Just zero out the stale constants to avoid the upload.
- */
- struct iris_shader_state *shs =
- &ice->state.shaders[MESA_SHADER_TESS_CTRL];
-
- memset(&shs->cbuf0, 0, sizeof(shs->cbuf0));
- }
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_TCS |
+ IRIS_STAGE_DIRTY_BINDINGS_TCS |
+ IRIS_STAGE_DIRTY_CONSTANTS_TCS;
+ shs->sysvals_need_upload = true;
}
}
static struct iris_compiled_shader *
iris_compile_tes(struct iris_context *ice,
struct iris_uncompiled_shader *ish,
- const struct brw_tes_prog_key *key)
+ const struct iris_tes_prog_key *key)
{
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
const struct brw_compiler *compiler = screen->compiler;
struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
enum brw_param_builtin *system_values;
+ const struct gen_device_info *devinfo = &screen->devinfo;
unsigned num_system_values;
unsigned num_cbufs;
nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
+ if (key->vue.nr_userclip_plane_consts) {
+ nir_function_impl *impl = nir_shader_get_entrypoint(nir);
+ nir_lower_clip_vs(nir, (1 << key->vue.nr_userclip_plane_consts) - 1,
+ true, false, NULL);
+ nir_lower_io_to_temporaries(nir, impl, true, false);
+ nir_lower_global_vars_to_local(nir);
+ nir_lower_vars_to_ssa(nir);
+ nir_shader_gather_info(nir, impl);
+ }
+
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
&num_system_values, &num_cbufs);
struct iris_binding_table bt;
- iris_setup_binding_table(nir, &bt, /* num_render_targets */ 0,
+ iris_setup_binding_table(devinfo, nir, &bt, /* num_render_targets */ 0,
num_system_values, num_cbufs);
brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
brw_compute_tess_vue_map(&input_vue_map, key->inputs_read,
key->patch_inputs_read);
+ struct brw_tes_prog_key brw_key = iris_to_brw_tes_key(devinfo, key);
+
char *error_str = NULL;
const unsigned *program =
- brw_compile_tes(compiler, &ice->dbg, mem_ctx, key, &input_vue_map,
- tes_prog_data, nir, NULL, -1, &error_str);
+ brw_compile_tes(compiler, &ice->dbg, mem_ctx, &brw_key, &input_vue_map,
+ tes_prog_data, nir, -1, NULL, &error_str);
if (program == NULL) {
dbg_printf("Failed to compile evaluation shader: %s\n", error_str);
ralloc_free(mem_ctx);
}
if (ish->compiled_once) {
- iris_debug_recompile(ice, &nir->info, key->program_string_id, key);
+ iris_debug_recompile(ice, &nir->info, &brw_key.base);
} else {
ish->compiled_once = true;
}
uint32_t *so_decls =
- ice->vtbl.create_so_decl_list(&ish->stream_output,
+ screen->vtbl.create_so_decl_list(&ish->stream_output,
&vue_prog_data->vue_map);
static void
iris_update_compiled_tes(struct iris_context *ice)
{
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_TESS_EVAL];
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
- struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_tes_prog_key key = { KEY_INIT(devinfo->gen) };
+ struct iris_tes_prog_key key = { KEY_ID(vue.base) };
get_unified_tess_slots(ice, &key.inputs_read, &key.patch_inputs_read);
- ice->vtbl.populate_tes_key(ice, &key);
+ screen->vtbl.populate_tes_key(ice, &ish->nir->info, last_vue_stage(ice), &key);
struct iris_compiled_shader *old = ice->shaders.prog[IRIS_CACHE_TES];
struct iris_compiled_shader *shader =
if (old != shader) {
ice->shaders.prog[IRIS_CACHE_TES] = shader;
- ice->state.dirty |= IRIS_DIRTY_TES |
- IRIS_DIRTY_BINDINGS_TES |
- IRIS_DIRTY_CONSTANTS_TES;
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_TES |
+ IRIS_STAGE_DIRTY_BINDINGS_TES |
+ IRIS_STAGE_DIRTY_CONSTANTS_TES;
+ shs->sysvals_need_upload = true;
}
/* TODO: Could compare and avoid flagging this. */
const struct shader_info *tes_info = &ish->nir->info;
if (tes_info->system_values_read & (1ull << SYSTEM_VALUE_VERTICES_IN)) {
- ice->state.dirty |= IRIS_DIRTY_CONSTANTS_TES;
- ice->state.shaders[MESA_SHADER_TESS_EVAL].cbuf0_needs_upload = true;
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_TES;
+ ice->state.shaders[MESA_SHADER_TESS_EVAL].sysvals_need_upload = true;
}
}
static struct iris_compiled_shader *
iris_compile_gs(struct iris_context *ice,
struct iris_uncompiled_shader *ish,
- const struct brw_gs_prog_key *key)
+ const struct iris_gs_prog_key *key)
{
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
const struct brw_compiler *compiler = screen->compiler;
nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
+ if (key->vue.nr_userclip_plane_consts) {
+ nir_function_impl *impl = nir_shader_get_entrypoint(nir);
+ nir_lower_clip_gs(nir, (1 << key->vue.nr_userclip_plane_consts) - 1,
+ false, NULL);
+ nir_lower_io_to_temporaries(nir, impl, true, false);
+ nir_lower_global_vars_to_local(nir);
+ nir_lower_vars_to_ssa(nir);
+ nir_shader_gather_info(nir, impl);
+ }
+
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
&num_system_values, &num_cbufs);
struct iris_binding_table bt;
- iris_setup_binding_table(nir, &bt, /* num_render_targets */ 0,
+ iris_setup_binding_table(devinfo, nir, &bt, /* num_render_targets */ 0,
num_system_values, num_cbufs);
brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
brw_compute_vue_map(devinfo,
&vue_prog_data->vue_map, nir->info.outputs_written,
- nir->info.separate_shader);
+ nir->info.separate_shader, /* pos_slots */ 1);
+
+ struct brw_gs_prog_key brw_key = iris_to_brw_gs_key(devinfo, key);
char *error_str = NULL;
const unsigned *program =
- brw_compile_gs(compiler, &ice->dbg, mem_ctx, key, gs_prog_data, nir,
- NULL, -1, &error_str);
+ brw_compile_gs(compiler, &ice->dbg, mem_ctx, &brw_key, gs_prog_data,
+ nir, NULL, -1, NULL, &error_str);
if (program == NULL) {
dbg_printf("Failed to compile geometry shader: %s\n", error_str);
ralloc_free(mem_ctx);
}
if (ish->compiled_once) {
- iris_debug_recompile(ice, &nir->info, key->program_string_id, key);
+ iris_debug_recompile(ice, &nir->info, &brw_key.base);
} else {
ish->compiled_once = true;
}
uint32_t *so_decls =
- ice->vtbl.create_so_decl_list(&ish->stream_output,
+ screen->vtbl.create_so_decl_list(&ish->stream_output,
&vue_prog_data->vue_map);
struct iris_compiled_shader *shader =
static void
iris_update_compiled_gs(struct iris_context *ice)
{
+ struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_GEOMETRY];
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_GEOMETRY];
struct iris_compiled_shader *old = ice->shaders.prog[IRIS_CACHE_GS];
struct iris_compiled_shader *shader = NULL;
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
if (ish) {
- struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_gs_prog_key key = { KEY_INIT(devinfo->gen) };
- ice->vtbl.populate_gs_key(ice, &key);
+ struct iris_gs_prog_key key = { KEY_ID(vue.base) };
+ screen->vtbl.populate_gs_key(ice, &ish->nir->info, last_vue_stage(ice), &key);
shader =
iris_find_cached_shader(ice, IRIS_CACHE_GS, sizeof(key), &key);
if (old != shader) {
ice->shaders.prog[IRIS_CACHE_GS] = shader;
- ice->state.dirty |= IRIS_DIRTY_GS |
- IRIS_DIRTY_BINDINGS_GS |
- IRIS_DIRTY_CONSTANTS_GS;
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_GS |
+ IRIS_STAGE_DIRTY_BINDINGS_GS |
+ IRIS_STAGE_DIRTY_CONSTANTS_GS;
+ shs->sysvals_need_upload = true;
}
}
static struct iris_compiled_shader *
iris_compile_fs(struct iris_context *ice,
struct iris_uncompiled_shader *ish,
- const struct brw_wm_prog_key *key,
+ const struct iris_fs_prog_key *key,
struct brw_vue_map *vue_map)
{
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
rzalloc(mem_ctx, struct brw_wm_prog_data);
struct brw_stage_prog_data *prog_data = &fs_prog_data->base;
enum brw_param_builtin *system_values;
+ const struct gen_device_info *devinfo = &screen->devinfo;
unsigned num_system_values;
unsigned num_cbufs;
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
&num_system_values, &num_cbufs);
+ /* Lower output variables to load_output intrinsics before setting up
+ * binding tables, so iris_setup_binding_table can map any load_output
+ * intrinsics to IRIS_SURFACE_GROUP_RENDER_TARGET_READ on Gen8 for
+ * non-coherent framebuffer fetches.
+ */
+ brw_nir_lower_fs_outputs(nir);
+
+ /* On Gen11+, shader RT write messages have a "Null Render Target" bit
+ * and do not need a binding table entry with a null surface. Earlier
+ * generations need an entry for a null surface.
+ */
+ int null_rts = devinfo->gen < 11 ? 1 : 0;
+
struct iris_binding_table bt;
- iris_setup_binding_table(nir, &bt, MAX2(key->nr_color_regions, 1),
+ iris_setup_binding_table(devinfo, nir, &bt,
+ MAX2(key->nr_color_regions, null_rts),
num_system_values, num_cbufs);
brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
+ struct brw_wm_prog_key brw_key = iris_to_brw_fs_key(devinfo, key);
+
char *error_str = NULL;
const unsigned *program =
- brw_compile_fs(compiler, &ice->dbg, mem_ctx, key, fs_prog_data,
- nir, NULL, -1, -1, -1, true, false, vue_map, &error_str);
+ brw_compile_fs(compiler, &ice->dbg, mem_ctx, &brw_key, fs_prog_data,
+ nir, -1, -1, -1, true, false, vue_map,
+ NULL, &error_str);
if (program == NULL) {
dbg_printf("Failed to compile fragment shader: %s\n", error_str);
ralloc_free(mem_ctx);
}
if (ish->compiled_once) {
- iris_debug_recompile(ice, &nir->info, key->program_string_id, key);
+ iris_debug_recompile(ice, &nir->info, &brw_key.base);
} else {
ish->compiled_once = true;
}
static void
iris_update_compiled_fs(struct iris_context *ice)
{
+ struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_FRAGMENT];
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
- struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_wm_prog_key key = { KEY_INIT(devinfo->gen) };
- ice->vtbl.populate_fs_key(ice, &key);
+ struct iris_fs_prog_key key = { KEY_ID(base) };
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ screen->vtbl.populate_fs_key(ice, &ish->nir->info, &key);
if (ish->nos & (1ull << IRIS_NOS_LAST_VUE_MAP))
key.input_slots_valid = ice->shaders.last_vue_map->slots_valid;
// XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
// toggles. might be able to avoid flagging SBE too.
ice->shaders.prog[IRIS_CACHE_FS] = shader;
- ice->state.dirty |= IRIS_DIRTY_FS |
- IRIS_DIRTY_BINDINGS_FS |
- IRIS_DIRTY_CONSTANTS_FS |
- IRIS_DIRTY_WM |
+ ice->state.dirty |= IRIS_DIRTY_WM |
IRIS_DIRTY_CLIP |
IRIS_DIRTY_SBE;
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_FS |
+ IRIS_STAGE_DIRTY_BINDINGS_FS |
+ IRIS_STAGE_DIRTY_CONSTANTS_FS;
+ shs->sysvals_need_upload = true;
}
}
-/**
- * Get the compiled shader for the last enabled geometry stage.
- *
- * This stage is the one which will feed stream output and the rasterizer.
- */
-static gl_shader_stage
-last_vue_stage(struct iris_context *ice)
-{
- if (ice->shaders.prog[MESA_SHADER_GEOMETRY])
- return MESA_SHADER_GEOMETRY;
-
- if (ice->shaders.prog[MESA_SHADER_TESS_EVAL])
- return MESA_SHADER_TESS_EVAL;
-
- return MESA_SHADER_VERTEX;
-}
-
/**
* Update the last enabled stage's VUE map.
*
(old_map ? old_map->slots_valid : 0ull) ^ vue_map->slots_valid;
if (changed_slots & VARYING_BIT_VIEWPORT) {
- // XXX: could use ctx->Const.MaxViewports for old API efficiency
ice->state.num_viewports =
(vue_map->slots_valid & VARYING_BIT_VIEWPORT) ? IRIS_MAX_VIEWPORTS : 1;
ice->state.dirty |= IRIS_DIRTY_CLIP |
IRIS_DIRTY_SF_CL_VIEWPORT |
IRIS_DIRTY_CC_VIEWPORT |
- IRIS_DIRTY_SCISSOR_RECT |
- IRIS_DIRTY_UNCOMPILED_FS |
- ice->state.dirty_for_nos[IRIS_NOS_LAST_VUE_MAP];
- // XXX: CC_VIEWPORT?
+ IRIS_DIRTY_SCISSOR_RECT;
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_UNCOMPILED_FS |
+ ice->state.stage_dirty_for_nos[IRIS_NOS_LAST_VUE_MAP];
}
if (changed_slots || (old_map && old_map->separate != vue_map->separate)) {
ice->shaders.last_vue_map = &vue_prog_data->vue_map;
}
+static void
+iris_update_pull_constant_descriptors(struct iris_context *ice,
+ gl_shader_stage stage)
+{
+ struct iris_compiled_shader *shader = ice->shaders.prog[stage];
+
+ if (!shader || !shader->prog_data->has_ubo_pull)
+ return;
+
+ struct iris_shader_state *shs = &ice->state.shaders[stage];
+ bool any_new_descriptors =
+ shader->num_system_values > 0 && shs->sysvals_need_upload;
+
+ unsigned bound_cbufs = shs->bound_cbufs;
+
+ while (bound_cbufs) {
+ const int i = u_bit_scan(&bound_cbufs);
+ struct pipe_shader_buffer *cbuf = &shs->constbuf[i];
+ struct iris_state_ref *surf_state = &shs->constbuf_surf_state[i];
+ if (!surf_state->res && cbuf->buffer) {
+ iris_upload_ubo_ssbo_surf_state(ice, cbuf, surf_state, false);
+ any_new_descriptors = true;
+ }
+ }
+
+ if (any_new_descriptors)
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_VS << stage;
+}
+
/**
* Get the prog_data for a given stage, or NULL if the stage is disabled.
*/
iris_update_compiled_shaders(struct iris_context *ice)
{
const uint64_t dirty = ice->state.dirty;
+ const uint64_t stage_dirty = ice->state.stage_dirty;
struct brw_vue_prog_data *old_prog_datas[4];
if (!(dirty & IRIS_DIRTY_URB)) {
old_prog_datas[i] = get_vue_prog_data(ice, i);
}
- if (dirty & (IRIS_DIRTY_UNCOMPILED_TCS | IRIS_DIRTY_UNCOMPILED_TES)) {
+ if (stage_dirty & (IRIS_STAGE_DIRTY_UNCOMPILED_TCS |
+ IRIS_STAGE_DIRTY_UNCOMPILED_TES)) {
struct iris_uncompiled_shader *tes =
ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
if (tes) {
} else {
ice->shaders.prog[IRIS_CACHE_TCS] = NULL;
ice->shaders.prog[IRIS_CACHE_TES] = NULL;
- ice->state.dirty |=
- IRIS_DIRTY_TCS | IRIS_DIRTY_TES |
- IRIS_DIRTY_BINDINGS_TCS | IRIS_DIRTY_BINDINGS_TES |
- IRIS_DIRTY_CONSTANTS_TCS | IRIS_DIRTY_CONSTANTS_TES;
+ ice->state.stage_dirty |=
+ IRIS_STAGE_DIRTY_TCS | IRIS_STAGE_DIRTY_TES |
+ IRIS_STAGE_DIRTY_BINDINGS_TCS | IRIS_STAGE_DIRTY_BINDINGS_TES |
+ IRIS_STAGE_DIRTY_CONSTANTS_TCS | IRIS_STAGE_DIRTY_CONSTANTS_TES;
}
}
- if (dirty & IRIS_DIRTY_UNCOMPILED_VS)
+ if (stage_dirty & IRIS_STAGE_DIRTY_UNCOMPILED_VS)
iris_update_compiled_vs(ice);
- if (dirty & IRIS_DIRTY_UNCOMPILED_GS)
+ if (stage_dirty & IRIS_STAGE_DIRTY_UNCOMPILED_GS)
iris_update_compiled_gs(ice);
- if (dirty & (IRIS_DIRTY_UNCOMPILED_GS | IRIS_DIRTY_UNCOMPILED_TES)) {
+ if (stage_dirty & (IRIS_STAGE_DIRTY_UNCOMPILED_GS |
+ IRIS_STAGE_DIRTY_UNCOMPILED_TES)) {
const struct iris_compiled_shader *gs =
ice->shaders.prog[MESA_SHADER_GEOMETRY];
const struct iris_compiled_shader *tes =
}
}
- if (dirty & IRIS_DIRTY_UNCOMPILED_FS)
+ if (stage_dirty & IRIS_STAGE_DIRTY_UNCOMPILED_FS)
iris_update_compiled_fs(ice);
/* Changing shader interfaces may require a URB configuration. */
}
}
}
+
+ for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_FRAGMENT; i++) {
+ if (ice->state.stage_dirty & (IRIS_STAGE_DIRTY_CONSTANTS_VS << i))
+ iris_update_pull_constant_descriptors(ice, i);
+ }
}
static struct iris_compiled_shader *
iris_compile_cs(struct iris_context *ice,
struct iris_uncompiled_shader *ish,
- const struct brw_cs_prog_key *key)
+ const struct iris_cs_prog_key *key)
{
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
const struct brw_compiler *compiler = screen->compiler;
rzalloc(mem_ctx, struct brw_cs_prog_data);
struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
enum brw_param_builtin *system_values;
+ const struct gen_device_info *devinfo = &screen->devinfo;
unsigned num_system_values;
unsigned num_cbufs;
nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
- prog_data->total_shared = nir->info.cs.shared_size;
+ NIR_PASS_V(nir, brw_nir_lower_cs_intrinsics);
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
&num_system_values, &num_cbufs);
struct iris_binding_table bt;
- iris_setup_binding_table(nir, &bt, /* num_render_targets */ 0,
+ iris_setup_binding_table(devinfo, nir, &bt, /* num_render_targets */ 0,
num_system_values, num_cbufs);
+ struct brw_cs_prog_key brw_key = iris_to_brw_cs_key(devinfo, key);
+
char *error_str = NULL;
const unsigned *program =
- brw_compile_cs(compiler, &ice->dbg, mem_ctx, key, cs_prog_data,
- nir, -1, &error_str);
+ brw_compile_cs(compiler, &ice->dbg, mem_ctx, &brw_key, cs_prog_data,
+ nir, -1, NULL, &error_str);
if (program == NULL) {
dbg_printf("Failed to compile compute shader: %s\n", error_str);
ralloc_free(mem_ctx);
}
if (ish->compiled_once) {
- iris_debug_recompile(ice, &nir->info, key->program_string_id, key);
+ iris_debug_recompile(ice, &nir->info, &brw_key.base);
} else {
ish->compiled_once = true;
}
return shader;
}
-void
-iris_update_compiled_compute_shader(struct iris_context *ice)
+static void
+iris_update_compiled_cs(struct iris_context *ice)
{
+ struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_COMPUTE];
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_COMPUTE];
+ struct iris_cs_prog_key key = { KEY_ID(base) };
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_cs_prog_key key = { KEY_INIT(devinfo->gen) };
- ice->vtbl.populate_cs_key(ice, &key);
+ screen->vtbl.populate_cs_key(ice, &key);
struct iris_compiled_shader *old = ice->shaders.prog[IRIS_CACHE_CS];
struct iris_compiled_shader *shader =
if (old != shader) {
ice->shaders.prog[IRIS_CACHE_CS] = shader;
- ice->state.dirty |= IRIS_DIRTY_CS |
- IRIS_DIRTY_BINDINGS_CS |
- IRIS_DIRTY_CONSTANTS_CS;
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CS |
+ IRIS_STAGE_DIRTY_BINDINGS_CS |
+ IRIS_STAGE_DIRTY_CONSTANTS_CS;
+ shs->sysvals_need_upload = true;
}
}
+void
+iris_update_compiled_compute_shader(struct iris_context *ice)
+{
+ if (ice->state.stage_dirty & IRIS_STAGE_DIRTY_UNCOMPILED_CS)
+ iris_update_compiled_cs(ice);
+
+ if (ice->state.stage_dirty & IRIS_STAGE_DIRTY_CONSTANTS_CS)
+ iris_update_pull_constant_descriptors(ice, MESA_SHADER_COMPUTE);
+}
+
void
iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
+ unsigned threads,
uint32_t *dst)
{
- assert(cs_prog_data->push.total.size > 0);
+ assert(brw_cs_push_const_total_size(cs_prog_data, threads) > 0);
assert(cs_prog_data->push.cross_thread.size == 0);
assert(cs_prog_data->push.per_thread.dwords == 1);
assert(cs_prog_data->base.param[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID);
- for (unsigned t = 0; t < cs_prog_data->threads; t++)
+ for (unsigned t = 0; t < threads; t++)
dst[8 * t] = t;
}
* as well. This is not currently documented at all.
*
* This hack is no longer necessary on Gen11+.
+ *
+ * For, Gen11+, scratch space allocation is based on the number of threads
+ * in the base configuration.
*/
unsigned subslice_total = screen->subslice_total;
- if (devinfo->gen < 11)
+ if (devinfo->gen >= 12)
+ subslice_total = devinfo->num_subslices[0];
+ else if (devinfo->gen == 11)
+ subslice_total = 8;
+ else if (devinfo->gen < 11)
subslice_total = 4 * devinfo->num_slices;
assert(subslice_total >= screen->subslice_total);
if (!*bop) {
unsigned scratch_ids_per_subslice = devinfo->max_cs_threads;
+
+ if (devinfo->gen >= 12) {
+ /* Same as ICL below, but with 16 EUs. */
+ scratch_ids_per_subslice = 16 * 8;
+ } else if (devinfo->gen == 11) {
+ /* The MEDIA_VFE_STATE docs say:
+ *
+ * "Starting with this configuration, the Maximum Number of
+ * Threads must be set to (#EU * 8) for GPGPU dispatches.
+ *
+ * Although there are only 7 threads per EU in the configuration,
+ * the FFTID is calculated as if there are 8 threads per EU,
+ * which in turn requires a larger amount of Scratch Space to be
+ * allocated by the driver."
+ */
+ scratch_ids_per_subslice = 8 * 8;
+ }
+
uint32_t max_threads[] = {
[MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
[MESA_SHADER_TESS_CTRL] = devinfo->max_tcs_threads,
if (!ish)
return NULL;
+ NIR_PASS(ish->needs_edge_flag, nir, iris_fix_edge_flags);
+
brw_preprocess_nir(screen->compiler, nir, NULL);
- NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo);
+ NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo,
+ &ish->uses_atomic_load_store);
NIR_PASS_V(nir, iris_lower_storage_image_derefs);
nir_sweep(nir);
if (screen->disk_cache) {
/* Serialize the NIR to a binary blob that we can hash for the disk
- * cache. First, drop unnecessary information (like variable names)
+ * cache. Drop unnecessary information (like variable names)
* so the serialized NIR is smaller, and also to let us detect more
- * isomorphic shaders when hashing, increasing cache hits. We clone
- * the NIR before stripping away this info because it can be useful
- * when inspecting and debugging shaders.
+ * isomorphic shaders when hashing, increasing cache hits.
*/
- nir_shader *clone = nir_shader_clone(NULL, nir);
- nir_strip(clone);
-
struct blob blob;
blob_init(&blob);
- nir_serialize(&blob, clone);
+ nir_serialize(&blob, nir, true);
_mesa_sha1_compute(blob.data, blob.size, ish->nir_sha1);
blob_finish(&blob);
-
- ralloc_free(clone);
}
return ish;
struct nir_shader *nir;
if (state->type == PIPE_SHADER_IR_TGSI)
- nir = tgsi_to_nir(state->tokens, ctx->screen);
+ nir = tgsi_to_nir(state->tokens, ctx->screen, false);
else
nir = state->ir.nir;
ish->nos |= (1ull << IRIS_NOS_RASTERIZER);
if (screen->precompile) {
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_vs_prog_key key = { KEY_INIT(devinfo->gen) };
+ struct iris_vs_prog_key key = { KEY_ID(vue.base) };
if (!iris_disk_cache_retrieve(ice, ish, &key, sizeof(key)))
iris_compile_vs(ice, ish, &key);
struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
struct shader_info *info = &ish->nir->info;
- // XXX: NOS?
-
if (screen->precompile) {
const unsigned _GL_TRIANGLES = 0x0004;
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_tcs_prog_key key = {
- KEY_INIT(devinfo->gen),
+ struct iris_tcs_prog_key key = {
+ KEY_ID(vue.base),
// XXX: make sure the linker fills this out from the TES...
.tes_primitive_mode =
info->tess.primitive_mode ? info->tess.primitive_mode
struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
struct shader_info *info = &ish->nir->info;
- // XXX: NOS?
+ /* User clip planes */
+ if (ish->nir->info.clip_distance_array_size == 0)
+ ish->nos |= (1ull << IRIS_NOS_RASTERIZER);
if (screen->precompile) {
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_tes_prog_key key = {
- KEY_INIT(devinfo->gen),
+ struct iris_tes_prog_key key = {
+ KEY_ID(vue.base),
// XXX: not ideal, need TCS output/TES input unification
.inputs_read = info->inputs_read,
.patch_inputs_read = info->patch_inputs_read,
struct iris_screen *screen = (void *) ctx->screen;
struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
- // XXX: NOS?
+ /* User clip planes */
+ if (ish->nir->info.clip_distance_array_size == 0)
+ ish->nos |= (1ull << IRIS_NOS_RASTERIZER);
if (screen->precompile) {
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_gs_prog_key key = { KEY_INIT(devinfo->gen) };
+ struct iris_gs_prog_key key = { KEY_ID(vue.base) };
if (!iris_disk_cache_retrieve(ice, ish, &key, sizeof(key)))
iris_compile_gs(ice, ish, &key);
util_bitcount64(info->inputs_read & BRW_FS_VARYING_INPUT_MASK) <= 16;
const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_wm_prog_key key = {
- KEY_INIT(devinfo->gen),
+ struct iris_fs_prog_key key = {
+ KEY_ID(base),
.nr_color_regions = util_bitcount(color_outputs),
- .coherent_fb_fetch = true,
+ .coherent_fb_fetch = devinfo->gen >= 9,
.input_slots_valid =
can_rearrange_varyings ? 0 : info->inputs_read | VARYING_BIT_POS,
};
// XXX: disallow more than 64KB of shared variables
if (screen->precompile) {
- const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_cs_prog_key key = { KEY_INIT(devinfo->gen) };
+ struct iris_cs_prog_key key = { KEY_ID(base) };
if (!iris_disk_cache_retrieve(ice, ish, &key, sizeof(key)))
iris_compile_cs(ice, ish, &key);
if (ice->shaders.uncompiled[stage] == ish) {
ice->shaders.uncompiled[stage] = NULL;
- ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_VS << stage;
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_UNCOMPILED_VS << stage;
}
if (ish->const_data) {
struct iris_uncompiled_shader *ish,
gl_shader_stage stage)
{
- uint64_t dirty_bit = IRIS_DIRTY_UNCOMPILED_VS << stage;
+ uint64_t stage_dirty_bit = IRIS_STAGE_DIRTY_UNCOMPILED_VS << stage;
const uint64_t nos = ish ? ish->nos : 0;
const struct shader_info *old_info = iris_get_shader_info(ice, stage);
if ((old_info ? util_last_bit(old_info->textures_used) : 0) !=
(new_info ? util_last_bit(new_info->textures_used) : 0)) {
- ice->state.dirty |= IRIS_DIRTY_SAMPLER_STATES_VS << stage;
+ ice->state.stage_dirty |= IRIS_STAGE_DIRTY_SAMPLER_STATES_VS << stage;
}
ice->shaders.uncompiled[stage] = ish;
- ice->state.dirty |= dirty_bit;
+ ice->state.stage_dirty |= stage_dirty_bit;
/* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
* (or that they no longer need to do so).
*/
for (int i = 0; i < IRIS_NOS_COUNT; i++) {
if (nos & (1 << i))
- ice->state.dirty_for_nos[i] |= dirty_bit;
+ ice->state.stage_dirty_for_nos[i] |= stage_dirty_bit;
else
- ice->state.dirty_for_nos[i] &= ~dirty_bit;
+ ice->state.stage_dirty_for_nos[i] &= ~stage_dirty_bit;
}
}
static void
iris_bind_vs_state(struct pipe_context *ctx, void *state)
{
+ struct iris_context *ice = (struct iris_context *)ctx;
+ struct iris_uncompiled_shader *new_ish = state;
+
+ if (new_ish &&
+ ice->state.window_space_position !=
+ new_ish->nir->info.vs.window_space_position) {
+ ice->state.window_space_position =
+ new_ish->nir->info.vs.window_space_position;
+
+ ice->state.dirty |= IRIS_DIRTY_CLIP |
+ IRIS_DIRTY_RASTER |
+ IRIS_DIRTY_CC_VIEWPORT;
+ }
+
bind_shader_state((void *) ctx, state, MESA_SHADER_VERTEX);
}
iris_bind_fs_state(struct pipe_context *ctx, void *state)
{
struct iris_context *ice = (struct iris_context *) ctx;
+ struct iris_screen *screen = (struct iris_screen *) ctx->screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
struct iris_uncompiled_shader *old_ish =
ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
struct iris_uncompiled_shader *new_ish = state;
(new_ish->nir->info.outputs_written & color_bits))
ice->state.dirty |= IRIS_DIRTY_PS_BLEND;
+ if (devinfo->gen == 8)
+ ice->state.dirty |= IRIS_DIRTY_PMA_FIX;
+
bind_shader_state((void *) ctx, state, MESA_SHADER_FRAGMENT);
}
projects / mesa.git / blobdiff