#include "util/os_memory.h"
#include "util/u_cpu_detect.h"
#include "util/u_inlines.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
#include "util/u_threaded_context.h"
#include "util/u_transfer.h"
#include "util/u_transfer_helper.h"
#include "iris_context.h"
#include "iris_resource.h"
#include "iris_screen.h"
+#include "intel/common/gen_aux_map.h"
#include "intel/dev/gen_debug.h"
#include "isl/isl.h"
#include "drm-uapi/drm_fourcc.h"
MODIFIER_PRIORITY_X,
MODIFIER_PRIORITY_Y,
MODIFIER_PRIORITY_Y_CCS,
+ MODIFIER_PRIORITY_Y_GEN12_RC_CCS,
};
static const uint64_t priority_to_modifier[] = {
[MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
[MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
[MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
+ [MODIFIER_PRIORITY_Y_GEN12_RC_CCS] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
};
static bool
modifier_is_supported(const struct gen_device_info *devinfo,
- uint64_t modifier)
+ enum pipe_format pfmt, uint64_t modifier)
{
- /* XXX: do something real */
+ /* Check for basic device support. */
switch (modifier) {
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_X_TILED:
case DRM_FORMAT_MOD_LINEAR:
- return true;
+ case I915_FORMAT_MOD_X_TILED:
+ case I915_FORMAT_MOD_Y_TILED:
+ break;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ if (devinfo->gen <= 8 || devinfo->gen >= 12)
+ return false;
+ break;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (devinfo->gen != 12)
+ return false;
+ break;
case DRM_FORMAT_MOD_INVALID:
default:
return false;
}
+
+ /* Check remaining requirements. */
+ switch (modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_CCS: {
+ if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC))
+ return false;
+
+ enum isl_format rt_format =
+ iris_format_for_usage(devinfo, pfmt,
+ ISL_SURF_USAGE_RENDER_TARGET_BIT).fmt;
+
+ if (rt_format == ISL_FORMAT_UNSUPPORTED ||
+ !isl_format_supports_ccs_e(devinfo, rt_format))
+ return false;
+ break;
+ }
+ default:
+ break;
+ }
+
+ return true;
}
static uint64_t
-select_best_modifier(struct gen_device_info *devinfo,
+select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt,
const uint64_t *modifiers,
int count)
{
enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
for (int i = 0; i < count; i++) {
- if (!modifier_is_supported(devinfo, modifiers[i]))
+ if (!modifier_is_supported(devinfo, pfmt, modifiers[i]))
continue;
switch (modifiers[i]) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ prio = MAX2(prio, MODIFIER_PRIORITY_Y_GEN12_RC_CCS);
+ break;
case I915_FORMAT_MOD_Y_TILED_CCS:
prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
break;
return priority_to_modifier[prio];
}
-static enum isl_surf_dim
+enum isl_surf_dim
target_to_isl_surf_dim(enum pipe_texture_target target)
{
switch (target) {
DRM_FORMAT_MOD_LINEAR,
I915_FORMAT_MOD_X_TILED,
I915_FORMAT_MOD_Y_TILED,
- // XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS,
+ I915_FORMAT_MOD_Y_TILED_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
};
int supported_mods = 0;
for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) {
- if (!modifier_is_supported(devinfo, all_modifiers[i]))
+ if (!modifier_is_supported(devinfo, pfmt, all_modifiers[i]))
continue;
if (supported_mods < max) {
*count = supported_mods;
}
-static isl_surf_usage_flags_t
-pipe_bind_to_isl_usage(unsigned bindings)
+enum isl_format
+iris_image_view_get_format(struct iris_context *ice,
+ const struct pipe_image_view *img)
{
- isl_surf_usage_flags_t usage = 0;
-
- if (bindings & PIPE_BIND_RENDER_TARGET)
- usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
-
- if (bindings & PIPE_BIND_SAMPLER_VIEW)
- usage |= ISL_SURF_USAGE_TEXTURE_BIT;
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
- if (bindings & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SHADER_BUFFER))
- usage |= ISL_SURF_USAGE_STORAGE_BIT;
+ isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
+ enum isl_format isl_fmt =
+ iris_format_for_usage(devinfo, img->format, usage).fmt;
- if (bindings & PIPE_BIND_DISPLAY_TARGET)
- usage |= ISL_SURF_USAGE_DISPLAY_BIT;
+ if (img->shader_access & PIPE_IMAGE_ACCESS_READ) {
+ /* On Gen8, try to use typed surfaces reads (which support a
+ * limited number of formats), and if not possible, fall back
+ * to untyped reads.
+ */
+ if (devinfo->gen == 8 &&
+ !isl_has_matching_typed_storage_image_format(devinfo, isl_fmt))
+ return ISL_FORMAT_RAW;
+ else
+ return isl_lower_storage_image_format(devinfo, isl_fmt);
+ }
- return usage;
+ return isl_fmt;
}
struct pipe_resource *
}
}
+enum isl_dim_layout
+iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
+ enum isl_tiling tiling,
+ enum pipe_texture_target target)
+{
+ switch (target) {
+ case PIPE_TEXTURE_1D:
+ case PIPE_TEXTURE_1D_ARRAY:
+ return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ?
+ ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D);
+
+ case PIPE_TEXTURE_2D:
+ case PIPE_TEXTURE_2D_ARRAY:
+ case PIPE_TEXTURE_RECT:
+ case PIPE_TEXTURE_CUBE:
+ case PIPE_TEXTURE_CUBE_ARRAY:
+ return ISL_DIM_LAYOUT_GEN4_2D;
+
+ case PIPE_TEXTURE_3D:
+ return (devinfo->gen >= 9 ?
+ ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D);
+
+ case PIPE_MAX_TEXTURE_TYPES:
+ case PIPE_BUFFER:
+ break;
+ }
+ unreachable("invalid texture type");
+}
+
void
iris_resource_disable_aux(struct iris_resource *res)
{
res->aux.usage = ISL_AUX_USAGE_NONE;
res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
+ res->aux.has_hiz = 0;
res->aux.surf.size_B = 0;
res->aux.bo = NULL;
+ res->aux.extra_aux.surf.size_B = 0;
res->aux.clear_color_bo = NULL;
res->aux.state = NULL;
}
iris_resource_disable_aux(res);
iris_bo_unreference(res->bo);
+ iris_pscreen_unref(res->base.screen);
+
free(res);
}
return NULL;
res->base = *templ;
- res->base.screen = pscreen;
+ res->base.screen = iris_pscreen_ref(pscreen);
pipe_reference_init(&res->base.reference, 1);
res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
static enum isl_aux_state **
create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
{
+ assert(res->aux.state == NULL);
+
uint32_t total_slices = 0;
for (uint32_t level = 0; level < res->surf.levels; level++)
total_slices += iris_get_num_logical_layers(res, level);
return per_level_arr;
}
+static unsigned
+iris_get_aux_clear_color_state_size(struct iris_screen *screen)
+{
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ return devinfo->gen >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0;
+}
+
+static void
+map_aux_addresses(struct iris_screen *screen, struct iris_resource *res)
+{
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ if (devinfo->gen >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) {
+ void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
+ assert(aux_map_ctx);
+ const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ?
+ res->aux.extra_aux.offset : res->aux.offset;
+ gen_aux_map_add_image(aux_map_ctx, &res->surf, res->bo->gtt_offset,
+ res->aux.bo->gtt_offset + aux_offset);
+ res->bo->aux_map_address = res->aux.bo->gtt_offset;
+ }
+}
+
+static bool
+want_ccs_e_for_format(const struct gen_device_info *devinfo,
+ enum isl_format format)
+{
+ if (!isl_format_supports_ccs_e(devinfo, format))
+ return false;
+
+ const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+
+ /* CCS_E seems to significantly hurt performance with 32-bit floating
+ * point formats. For example, Paraview's "Wavelet Volume" case uses
+ * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
+ * formats causes a 62% FPS drop.
+ *
+ * However, many benchmarks seem to use 16-bit float with no issues.
+ */
+ if (fmtl->channels.r.bits == 32 && fmtl->channels.r.type == ISL_SFLOAT)
+ return false;
+
+ return true;
+}
+
+static bool
+iris_resource_configure_main(const struct iris_screen *screen,
+ struct iris_resource *res,
+ const struct pipe_resource *templ,
+ uint64_t modifier, uint32_t row_pitch_B)
+{
+ res->mod_info = isl_drm_modifier_get_info(modifier);
+
+ if (modifier != DRM_FORMAT_MOD_INVALID && res->mod_info == NULL)
+ return false;
+
+ isl_tiling_flags_t tiling_flags = 0;
+
+ if (res->mod_info != NULL) {
+ tiling_flags = 1 << res->mod_info->tiling;
+ } else if (templ->usage == PIPE_USAGE_STAGING ||
+ templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR)) {
+ tiling_flags = ISL_TILING_LINEAR_BIT;
+ } else if (templ->bind & PIPE_BIND_SCANOUT) {
+ tiling_flags = screen->devinfo.has_tiling_uapi ?
+ ISL_TILING_X_BIT : ISL_TILING_LINEAR_BIT;
+ } else {
+ tiling_flags = ISL_TILING_ANY_MASK;
+ }
+
+ isl_surf_usage_flags_t usage = 0;
+
+ if (templ->bind & PIPE_BIND_RENDER_TARGET)
+ usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
+
+ if (templ->bind & PIPE_BIND_SAMPLER_VIEW)
+ usage |= ISL_SURF_USAGE_TEXTURE_BIT;
+
+ if (templ->bind & PIPE_BIND_SHADER_IMAGE)
+ usage |= ISL_SURF_USAGE_STORAGE_BIT;
+
+ if (templ->bind & PIPE_BIND_SCANOUT)
+ usage |= ISL_SURF_USAGE_DISPLAY_BIT;
+
+ if (templ->target == PIPE_TEXTURE_CUBE ||
+ templ->target == PIPE_TEXTURE_CUBE_ARRAY) {
+ usage |= ISL_SURF_USAGE_CUBE_BIT;
+ }
+
+ if (templ->usage != PIPE_USAGE_STAGING &&
+ util_format_is_depth_or_stencil(templ->format)) {
+
+ /* Should be handled by u_transfer_helper */
+ assert(!util_format_is_depth_and_stencil(templ->format));
+
+ usage |= templ->format == PIPE_FORMAT_S8_UINT ?
+ ISL_SURF_USAGE_STENCIL_BIT : ISL_SURF_USAGE_DEPTH_BIT;
+ }
+
+ const enum isl_format format =
+ iris_format_for_usage(&screen->devinfo, templ->format, usage).fmt;
+
+ const struct isl_surf_init_info init_info = {
+ .dim = target_to_isl_surf_dim(templ->target),
+ .format = format,
+ .width = templ->width0,
+ .height = templ->height0,
+ .depth = templ->depth0,
+ .levels = templ->last_level + 1,
+ .array_len = templ->array_size,
+ .samples = MAX2(templ->nr_samples, 1),
+ .min_alignment_B = 0,
+ .row_pitch_B = row_pitch_B,
+ .usage = usage,
+ .tiling_flags = tiling_flags
+ };
+
+ if (!isl_surf_init_s(&screen->isl_dev, &res->surf, &init_info))
+ return false;
+
+ res->internal_format = templ->format;
+
+ return true;
+}
+
/**
- * Allocate the initial aux surface for a resource based on aux.usage
+ * Configure aux for the resource, but don't allocate it. For images which
+ * might be shared with modifiers, we must allocate the image and aux data in
+ * a single bo.
+ *
+ * Returns false on unexpected error (e.g. allocation failed, or invalid
+ * configuration result).
*/
static bool
-iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res)
+iris_resource_configure_aux(struct iris_screen *screen,
+ struct iris_resource *res, bool imported)
{
- struct isl_device *isl_dev = &screen->isl_dev;
- enum isl_aux_state initial_state;
- UNUSED bool ok = false;
- uint8_t memset_value = 0;
- uint32_t alloc_flags = 0;
const struct gen_device_info *devinfo = &screen->devinfo;
- const unsigned clear_color_state_size = devinfo->gen >= 10 ?
- screen->isl_dev.ss.clear_color_state_size :
- (devinfo->gen >= 9 ? screen->isl_dev.ss.clear_value_size : 0);
+ /* Try to create the auxiliary surfaces allowed by the modifier or by
+ * the user if no modifier is specified.
+ */
+ assert(!res->mod_info ||
+ res->mod_info->aux_usage == ISL_AUX_USAGE_NONE ||
+ res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ res->mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E);
+
+ const bool has_mcs = !res->mod_info &&
+ isl_surf_get_mcs_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
+
+ const bool has_hiz = !res->mod_info && !(INTEL_DEBUG & DEBUG_NO_HIZ) &&
+ isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
+
+ const bool has_ccs =
+ ((!res->mod_info && !(INTEL_DEBUG & DEBUG_NO_RBC)) ||
+ (res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE)) &&
+ isl_surf_get_ccs_surf(&screen->isl_dev, &res->surf, &res->aux.surf,
+ &res->aux.extra_aux.surf, 0);
+
+ /* Having both HIZ and MCS is impossible. */
+ assert(!has_mcs || !has_hiz);
+
+ /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
+ if (has_ccs && (has_mcs || has_hiz)) {
+ assert(res->aux.extra_aux.surf.size_B > 0 &&
+ res->aux.extra_aux.surf.usage & ISL_SURF_USAGE_CCS_BIT);
+ assert(res->aux.surf.size_B > 0 &&
+ res->aux.surf.usage &
+ (ISL_SURF_USAGE_HIZ_BIT | ISL_SURF_USAGE_MCS_BIT));
+ }
+
+ if (res->mod_info && has_ccs) {
+ /* Only allow a CCS modifier if the aux was created successfully. */
+ res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
+ } else if (has_mcs) {
+ res->aux.possible_usages |=
+ 1 << (has_ccs ? ISL_AUX_USAGE_MCS_CCS : ISL_AUX_USAGE_MCS);
+ } else if (has_hiz) {
+ if (!has_ccs) {
+ res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
+ } else if (res->surf.samples == 1 &&
+ (res->surf.usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
+ /* If this resource is single-sampled and will be used as a texture,
+ * put the HiZ surface in write-through mode so that we can sample
+ * from it.
+ */
+ res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS_WT;
+ } else {
+ res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS;
+ }
+ } else if (has_ccs && isl_surf_usage_is_stencil(res->surf.usage)) {
+ res->aux.possible_usages |= 1 << ISL_AUX_USAGE_STC_CCS;
+ } else if (has_ccs) {
+ if (want_ccs_e_for_format(devinfo, res->surf.format)) {
+ res->aux.possible_usages |= devinfo->gen < 12 ?
+ 1 << ISL_AUX_USAGE_CCS_E : 1 << ISL_AUX_USAGE_GEN12_CCS_E;
+ } else if (isl_format_supports_ccs_d(devinfo, res->surf.format)) {
+ res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
+ }
+ }
+
+ res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;
+
+ res->aux.sampler_usages = res->aux.possible_usages;
+
+ /* We don't always support sampling with hiz. But when we do, it must be
+ * single sampled.
+ */
+ if (!devinfo->has_sample_with_hiz || res->surf.samples > 1)
+ res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
+
+ /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
+ res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ_CCS);
+
+ enum isl_aux_state initial_state;
assert(!res->aux.bo);
switch (res->aux.usage) {
case ISL_AUX_USAGE_NONE:
- res->aux.surf.size_B = 0;
- ok = true;
- break;
+ /* Update relevant fields to indicate that aux is disabled. */
+ iris_resource_disable_aux(res);
+
+ /* Having no aux buffer is only okay if there's no modifier with aux. */
+ return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE;
case ISL_AUX_USAGE_HIZ:
+ case ISL_AUX_USAGE_HIZ_CCS:
+ case ISL_AUX_USAGE_HIZ_CCS_WT:
initial_state = ISL_AUX_STATE_AUX_INVALID;
- memset_value = 0;
- ok = isl_surf_get_hiz_surf(isl_dev, &res->surf, &res->aux.surf);
break;
case ISL_AUX_USAGE_MCS:
+ case ISL_AUX_USAGE_MCS_CCS:
/* The Ivybridge PRM, Vol 2 Part 1 p326 says:
*
* "When MCS buffer is enabled and bound to MSRT, it is required
* 1's, so we simply memset it to 0xff.
*/
initial_state = ISL_AUX_STATE_CLEAR;
- memset_value = 0xFF;
- ok = isl_surf_get_mcs_surf(isl_dev, &res->surf, &res->aux.surf);
break;
case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E:
+ case ISL_AUX_USAGE_GEN12_CCS_E:
+ case ISL_AUX_USAGE_STC_CCS:
/* When CCS_E is used, we need to ensure that the CCS starts off in
* a valid state. From the Sky Lake PRM, "MCS Buffer for Render
* Target(s)":
* For CCS_D, do the same thing. On Gen9+, this avoids having any
* undefined bits in the aux buffer.
*/
- initial_state = ISL_AUX_STATE_PASS_THROUGH;
- alloc_flags |= BO_ALLOC_ZEROED;
- ok = isl_surf_get_ccs_surf(isl_dev, &res->surf, &res->aux.surf, 0);
+ if (imported) {
+ assert(res->aux.usage != ISL_AUX_USAGE_STC_CCS);
+ initial_state =
+ isl_drm_modifier_get_default_aux_state(res->mod_info->modifier);
+ } else {
+ initial_state = ISL_AUX_STATE_PASS_THROUGH;
+ }
break;
+ case ISL_AUX_USAGE_MC:
+ default:
+ unreachable("Unsupported aux mode");
}
- /* We should have a valid aux_surf. */
- if (!ok)
- return false;
-
- /* No work is needed for a zero-sized auxiliary buffer. */
- if (res->aux.surf.size_B == 0)
- return true;
-
/* Create the aux_state for the auxiliary buffer. */
res->aux.state = create_aux_state_map(res, initial_state);
if (!res->aux.state)
return false;
- uint64_t size = res->aux.surf.size_B;
-
- /* Allocate space in the buffer for storing the clear color. On modern
- * platforms (gen > 9), we can read it directly from such buffer.
- *
- * On gen <= 9, we are going to store the clear color on the buffer
- * anyways, and copy it back to the surface state during state emission.
- */
- res->aux.clear_color_offset = size;
- size += clear_color_state_size;
-
- /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
- * the drm allocator. Therefore, one can pass the ISL dimensions in terms
- * of bytes instead of trying to recalculate based on different format
- * block sizes.
- */
- res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size,
- IRIS_MEMZONE_OTHER, I915_TILING_Y,
- res->aux.surf.row_pitch_B, alloc_flags);
- if (!res->aux.bo) {
- return false;
- }
-
- if (!(alloc_flags & BO_ALLOC_ZEROED)) {
- void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
-
- if (!map) {
- iris_resource_disable_aux(res);
- return false;
- }
-
- if (memset_value != 0)
- memset(map, memset_value, res->aux.surf.size_B);
-
- /* Zero the indirect clear color to match ::fast_clear_color. */
- memset((char *)map + res->aux.clear_color_offset, 0,
- clear_color_state_size);
-
- iris_bo_unmap(res->aux.bo);
- }
-
- if (clear_color_state_size > 0) {
- res->aux.clear_color_bo = res->aux.bo;
- iris_bo_reference(res->aux.clear_color_bo);
- }
-
- if (res->aux.usage == ISL_AUX_USAGE_HIZ) {
+ if (isl_aux_usage_has_hiz(res->aux.usage)) {
for (unsigned level = 0; level < res->surf.levels; ++level) {
uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
return true;
}
+/**
+ * Initialize the aux buffer contents.
+ *
+ * Returns false on unexpected error (e.g. mapping a BO failed).
+ */
static bool
-supports_mcs(const struct isl_surf *surf)
+iris_resource_init_aux_buf(struct iris_resource *res,
+ unsigned clear_color_state_size)
{
- /* MCS compression only applies to multisampled resources. */
- if (surf->samples <= 1)
- return false;
+ void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
- /* Depth and stencil buffers use the IMS (interleaved) layout. */
- if (isl_surf_usage_is_depth_or_stencil(surf->usage))
+ if (!map)
return false;
+ if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID) {
+ /* See iris_resource_configure_aux for the memset_value rationale. */
+ uint8_t memset_value = isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0;
+ memset((char*)map + res->aux.offset, memset_value,
+ res->aux.surf.size_B);
+ }
+
+ memset((char*)map + res->aux.extra_aux.offset,
+ 0, res->aux.extra_aux.surf.size_B);
+
+ /* Zero the indirect clear color to match ::fast_clear_color. */
+ memset((char *)map + res->aux.clear_color_offset, 0,
+ clear_color_state_size);
+
+ iris_bo_unmap(res->aux.bo);
+
+ if (clear_color_state_size > 0) {
+ res->aux.clear_color_bo = res->aux.bo;
+ iris_bo_reference(res->aux.clear_color_bo);
+ }
+
return true;
}
-static bool
-supports_ccs(const struct gen_device_info *devinfo,
- const struct isl_surf *surf)
+void
+iris_resource_finish_aux_import(struct pipe_screen *pscreen,
+ struct iris_resource *res)
{
- /* CCS only supports singlesampled resources. */
- if (surf->samples > 1)
- return false;
+ struct iris_screen *screen = (struct iris_screen *)pscreen;
+ assert(iris_resource_unfinished_aux_import(res));
+ assert(!res->mod_info->supports_clear_color);
- /* Note: still need to check the format! */
+ struct iris_resource *aux_res = (void *) res->base.next;
+ assert(aux_res->aux.surf.row_pitch_B && aux_res->aux.offset &&
+ aux_res->aux.bo);
- return true;
+ assert(res->bo == aux_res->aux.bo);
+ iris_bo_reference(aux_res->aux.bo);
+ res->aux.bo = aux_res->aux.bo;
+
+ res->aux.offset = aux_res->aux.offset;
+
+ assert(res->bo->size >= (res->aux.offset + res->aux.surf.size_B));
+ assert(res->aux.clear_color_bo == NULL);
+
+ assert(aux_res->aux.surf.row_pitch_B == res->aux.surf.row_pitch_B);
+
+ unsigned clear_color_state_size =
+ iris_get_aux_clear_color_state_size(screen);
+
+ if (clear_color_state_size > 0) {
+ res->aux.clear_color_bo =
+ iris_bo_alloc_tiled(screen->bufmgr, "clear color_buffer",
+ clear_color_state_size, 1, IRIS_MEMZONE_OTHER,
+ I915_TILING_NONE, 0, BO_ALLOC_ZEROED);
+ }
+
+ iris_resource_destroy(&screen->base, res->base.next);
+ res->base.next = NULL;
+
+ map_aux_addresses(screen, res);
}
static struct pipe_resource *
return NULL;
}
+ if (templ->bind & PIPE_BIND_SHARED)
+ iris_bo_make_external(res->bo);
+
return &res->base;
}
if (!res)
return NULL;
- const struct util_format_description *format_desc =
- util_format_description(templ->format);
- const bool has_depth = util_format_has_depth(format_desc);
uint64_t modifier =
- select_best_modifier(devinfo, modifiers, modifiers_count);
-
- isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
-
- if (modifier != DRM_FORMAT_MOD_INVALID) {
- res->mod_info = isl_drm_modifier_get_info(modifier);
-
- tiling_flags = 1 << res->mod_info->tiling;
- } else {
- if (modifiers_count > 0) {
- fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
- return NULL;
- }
-
- /* No modifiers - we can select our own tiling. */
-
- if (has_depth) {
- /* Depth must be Y-tiled */
- tiling_flags = ISL_TILING_Y0_BIT;
- } else if (templ->format == PIPE_FORMAT_S8_UINT) {
- /* Stencil must be W-tiled */
- tiling_flags = ISL_TILING_W_BIT;
- } else if (templ->target == PIPE_BUFFER ||
- templ->target == PIPE_TEXTURE_1D ||
- templ->target == PIPE_TEXTURE_1D_ARRAY) {
- /* Use linear for buffers and 1D textures */
- tiling_flags = ISL_TILING_LINEAR_BIT;
- }
-
- /* Use linear for staging buffers */
- if (templ->usage == PIPE_USAGE_STAGING ||
- templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) )
- tiling_flags = ISL_TILING_LINEAR_BIT;
- }
-
- isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind);
+ select_best_modifier(devinfo, templ->format, modifiers, modifiers_count);
- if (templ->target == PIPE_TEXTURE_CUBE ||
- templ->target == PIPE_TEXTURE_CUBE_ARRAY)
- usage |= ISL_SURF_USAGE_CUBE_BIT;
-
- if (templ->usage != PIPE_USAGE_STAGING) {
- if (templ->format == PIPE_FORMAT_S8_UINT)
- usage |= ISL_SURF_USAGE_STENCIL_BIT;
- else if (has_depth)
- usage |= ISL_SURF_USAGE_DEPTH_BIT;
+ if (modifier == DRM_FORMAT_MOD_INVALID && modifiers_count > 0) {
+ fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
+ goto fail;
}
- enum pipe_format pfmt = templ->format;
- res->internal_format = pfmt;
-
- /* Should be handled by u_transfer_helper */
- assert(!util_format_is_depth_and_stencil(pfmt));
-
- struct iris_format_info fmt = iris_format_for_usage(devinfo, pfmt, usage);
- assert(fmt.fmt != ISL_FORMAT_UNSUPPORTED);
-
UNUSED const bool isl_surf_created_successfully =
- isl_surf_init(&screen->isl_dev, &res->surf,
- .dim = target_to_isl_surf_dim(templ->target),
- .format = fmt.fmt,
- .width = templ->width0,
- .height = templ->height0,
- .depth = templ->depth0,
- .levels = templ->last_level + 1,
- .array_len = templ->array_size,
- .samples = MAX2(templ->nr_samples, 1),
- .min_alignment_B = 0,
- .row_pitch_B = 0,
- .usage = usage,
- .tiling_flags = tiling_flags);
+ iris_resource_configure_main(screen, res, templ, modifier, 0);
assert(isl_surf_created_successfully);
- if (res->mod_info) {
- res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
- } else if (supports_mcs(&res->surf)) {
- res->aux.possible_usages |= 1 << ISL_AUX_USAGE_MCS;
- } else if (has_depth) {
- if (likely(!(INTEL_DEBUG & DEBUG_NO_HIZ)))
- res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
- } else if (likely(!(INTEL_DEBUG & DEBUG_NO_RBC)) &&
- supports_ccs(devinfo, &res->surf)) {
- if (isl_format_supports_ccs_e(devinfo, res->surf.format))
- res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E;
-
- if (isl_format_supports_ccs_d(devinfo, res->surf.format))
- res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
- }
-
- res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;
-
- res->aux.sampler_usages = res->aux.possible_usages;
-
- /* We don't always support sampling with hiz. But when we do, it must be
- * single sampled.
- */
- if (!devinfo->has_sample_with_hiz || res->surf.samples > 1) {
- res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
- }
-
const char *name = "miptree";
enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE)));
- res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, res->surf.size_B,
+ if (!iris_resource_configure_aux(screen, res, false))
+ goto fail;
+
+ /* Modifiers require the aux data to be in the same buffer as the main
+ * surface, but we combine them even when a modifier is not being used.
+ */
+ uint64_t bo_size = res->surf.size_B;
+
+ /* Allocate space for the aux buffer. */
+ if (res->aux.surf.size_B > 0) {
+ res->aux.offset = ALIGN(bo_size, res->aux.surf.alignment_B);
+ bo_size = res->aux.offset + res->aux.surf.size_B;
+ }
+
+ /* Allocate space for the extra aux buffer. */
+ if (res->aux.extra_aux.surf.size_B > 0) {
+ res->aux.extra_aux.offset =
+ ALIGN(bo_size, res->aux.extra_aux.surf.alignment_B);
+ bo_size = res->aux.extra_aux.offset + res->aux.extra_aux.surf.size_B;
+ }
+
+ /* Allocate space for the indirect clear color.
+ *
+ * Also add some padding to make sure the fast clear color state buffer
+ * starts at a 4K alignment. We believe that 256B might be enough, but due
+ * to lack of testing we will leave this as 4K for now.
+ */
+ if (res->aux.surf.size_B > 0) {
+ res->aux.clear_color_offset = ALIGN(bo_size, 4096);
+ bo_size = res->aux.clear_color_offset +
+ iris_get_aux_clear_color_state_size(screen);
+ }
+
+ uint32_t alignment = MAX2(4096, res->surf.alignment_B);
+ res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, bo_size, alignment,
memzone,
isl_tiling_to_i915_tiling(res->surf.tiling),
res->surf.row_pitch_B, flags);
if (!res->bo)
goto fail;
- if (!iris_resource_alloc_aux(screen, res))
- iris_resource_disable_aux(res);
+ if (res->aux.surf.size_B > 0) {
+ res->aux.bo = res->bo;
+ iris_bo_reference(res->aux.bo);
+ unsigned clear_color_state_size =
+ iris_get_aux_clear_color_state_size(screen);
+ if (!iris_resource_init_aux_buf(res, clear_color_state_size))
+ goto fail;
+ map_aux_addresses(screen, res);
+ }
+
+ if (templ->bind & PIPE_BIND_SHARED)
+ iris_bo_make_external(res->bo);
return &res->base;
user_memory, templ->width0,
IRIS_MEMZONE_OTHER);
if (!res->bo) {
- free(res);
+ iris_resource_destroy(pscreen, &res->base);
return NULL;
}
- util_range_add(&res->valid_buffer_range, 0, templ->width0);
+ util_range_add(&res->base, &res->valid_buffer_range, 0, templ->width0);
return &res->base;
}
struct winsys_handle *whandle,
unsigned usage)
{
+ assert(templ->target != PIPE_BUFFER);
+
struct iris_screen *screen = (struct iris_screen *)pscreen;
- struct gen_device_info *devinfo = &screen->devinfo;
struct iris_bufmgr *bufmgr = screen->bufmgr;
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
if (!res)
switch (whandle->type) {
case WINSYS_HANDLE_TYPE_FD:
- res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle);
+ res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle,
+ whandle->modifier);
break;
case WINSYS_HANDLE_TYPE_SHARED:
res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
unreachable("invalid winsys handle type");
}
if (!res->bo)
- return NULL;
+ goto fail;
res->offset = whandle->offset;
+ res->external_format = whandle->format;
- uint64_t modifier = whandle->modifier;
- if (modifier == DRM_FORMAT_MOD_INVALID) {
- modifier = tiling_to_modifier(res->bo->tiling_mode);
- }
- res->mod_info = isl_drm_modifier_get_info(modifier);
- assert(res->mod_info);
-
- isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind);
+ /* Create a surface for each plane specified by the external format. */
+ if (whandle->plane < util_format_get_num_planes(whandle->format)) {
- const struct iris_format_info fmt =
- iris_format_for_usage(devinfo, templ->format, isl_usage);
- res->internal_format = templ->format;
-
- if (templ->target == PIPE_BUFFER) {
- res->surf.tiling = ISL_TILING_LINEAR;
- } else {
- isl_surf_init(&screen->isl_dev, &res->surf,
- .dim = target_to_isl_surf_dim(templ->target),
- .format = fmt.fmt,
- .width = templ->width0,
- .height = templ->height0,
- .depth = templ->depth0,
- .levels = templ->last_level + 1,
- .array_len = templ->array_size,
- .samples = MAX2(templ->nr_samples, 1),
- .min_alignment_B = 0,
- .row_pitch_B = whandle->stride,
- .usage = isl_usage,
- .tiling_flags = 1 << res->mod_info->tiling);
+ const uint64_t modifier =
+ whandle->modifier != DRM_FORMAT_MOD_INVALID ?
+ whandle->modifier : tiling_to_modifier(res->bo->tiling_mode);
+ UNUSED const bool isl_surf_created_successfully =
+ iris_resource_configure_main(screen, res, templ, modifier,
+ whandle->stride);
+ assert(isl_surf_created_successfully);
assert(res->bo->tiling_mode ==
isl_tiling_to_i915_tiling(res->surf.tiling));
- // XXX: create_ccs_buf_for_image?
- if (!iris_resource_alloc_aux(screen, res))
- goto fail;
+ UNUSED const bool ok = iris_resource_configure_aux(screen, res, true);
+ assert(ok);
+ /* The gallium dri layer will create a separate plane resource for the
+ * aux image. iris_resource_finish_aux_import will merge the separate aux
+ * parameters back into a single iris_resource.
+ */
+ } else {
+ /* Save modifier import information to reconstruct later. After import,
+ * this will be available under a second image accessible from the main
+ * image with res->base.next. See iris_resource_finish_aux_import.
+ */
+ res->aux.surf.row_pitch_B = whandle->stride;
+ res->aux.offset = whandle->offset;
+ res->aux.bo = res->bo;
+ res->bo = NULL;
}
return &res->base;
iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
{
struct iris_context *ice = (struct iris_context *)ctx;
- struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER];
struct iris_resource *res = (void *) resource;
const struct isl_drm_modifier_info *mod = res->mod_info;
- iris_resource_prepare_access(ice, render_batch, res,
+ iris_resource_prepare_access(ice, res,
0, INTEL_REMAINING_LEVELS,
0, INTEL_REMAINING_LAYERS,
mod ? mod->aux_usage : ISL_AUX_USAGE_NONE,
mod ? mod->supports_clear_color : false);
}
-static boolean
+static void
+iris_resource_disable_aux_on_first_query(struct pipe_resource *resource,
+ unsigned usage)
+{
+ struct iris_resource *res = (struct iris_resource *)resource;
+ bool mod_with_aux =
+ res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
+
+ /* Disable aux usage if explicit flush not set and this is the first time
+ * we are dealing with this resource and the resource was not created with
+ * a modifier with aux.
+ */
+ if (!mod_with_aux &&
+ (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) &&
+ p_atomic_read(&resource->reference.count) == 1) {
+ iris_resource_disable_aux(res);
+ }
+}
+
+static bool
+iris_resource_get_param(struct pipe_screen *pscreen,
+ struct pipe_context *context,
+ struct pipe_resource *resource,
+ unsigned plane,
+ unsigned layer,
+ enum pipe_resource_param param,
+ unsigned handle_usage,
+ uint64_t *value)
+{
+ struct iris_screen *screen = (struct iris_screen *)pscreen;
+ struct iris_resource *res = (struct iris_resource *)resource;
+ bool mod_with_aux =
+ res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
+ bool wants_aux = mod_with_aux && plane > 0;
+ bool result;
+ unsigned handle;
+
+ if (iris_resource_unfinished_aux_import(res))
+ iris_resource_finish_aux_import(pscreen, res);
+
+ struct iris_bo *bo = wants_aux ? res->aux.bo : res->bo;
+
+ iris_resource_disable_aux_on_first_query(resource, handle_usage);
+
+ switch (param) {
+ case PIPE_RESOURCE_PARAM_NPLANES:
+ if (mod_with_aux) {
+ *value = 2;
+ } else {
+ unsigned count = 0;
+ for (struct pipe_resource *cur = resource; cur; cur = cur->next)
+ count++;
+ *value = count;
+ }
+ return true;
+ case PIPE_RESOURCE_PARAM_STRIDE:
+ *value = wants_aux ? res->aux.surf.row_pitch_B : res->surf.row_pitch_B;
+ return true;
+ case PIPE_RESOURCE_PARAM_OFFSET:
+ *value = wants_aux ? res->aux.offset : 0;
+ return true;
+ case PIPE_RESOURCE_PARAM_MODIFIER:
+ *value = res->mod_info ? res->mod_info->modifier :
+ tiling_to_modifier(res->bo->tiling_mode);
+ return true;
+ case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED:
+ result = iris_bo_flink(bo, &handle) == 0;
+ if (result)
+ *value = handle;
+ return result;
+ case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: {
+ /* Because we share the same drm file across multiple iris_screen, when
+ * we export a GEM handle we must make sure it is valid in the DRM file
+ * descriptor the caller is using (this is the FD given at screen
+ * creation).
+ */
+ uint32_t handle;
+ if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
+ return false;
+ *value = handle;
+ return true;
+ }
+
+ case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD:
+ result = iris_bo_export_dmabuf(bo, (int *) &handle) == 0;
+ if (result)
+ *value = handle;
+ return result;
+ default:
+ return false;
+ }
+}
+
+static bool
iris_resource_get_handle(struct pipe_screen *pscreen,
struct pipe_context *ctx,
struct pipe_resource *resource,
struct winsys_handle *whandle,
unsigned usage)
{
+ struct iris_screen *screen = (struct iris_screen *) pscreen;
struct iris_resource *res = (struct iris_resource *)resource;
+ bool mod_with_aux =
+ res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
- /* Disable aux usage if explicit flush not set and this is the
- * first time we are dealing with this resource.
- */
- if ((!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0)) {
- if (p_atomic_read(&resource->reference.count) == 1)
- iris_resource_disable_aux(res);
+ iris_resource_disable_aux_on_first_query(resource, usage);
+
+ struct iris_bo *bo;
+ if (mod_with_aux && whandle->plane > 0) {
+ assert(res->aux.bo);
+ bo = res->aux.bo;
+ whandle->stride = res->aux.surf.row_pitch_B;
+ whandle->offset = res->aux.offset;
+ } else {
+ /* If this is a buffer, stride should be 0 - no need to special case */
+ whandle->stride = res->surf.row_pitch_B;
+ bo = res->bo;
}
- /* If this is a buffer, stride should be 0 - no need to special case */
- whandle->stride = res->surf.row_pitch_B;
+ whandle->format = res->external_format;
whandle->modifier =
res->mod_info ? res->mod_info->modifier
: tiling_to_modifier(res->bo->tiling_mode);
#ifndef NDEBUG
enum isl_aux_usage allowed_usage =
+ usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH ? res->aux.usage :
res->mod_info ? res->mod_info->aux_usage : ISL_AUX_USAGE_NONE;
if (res->aux.usage != allowed_usage) {
switch (whandle->type) {
case WINSYS_HANDLE_TYPE_SHARED:
- return iris_bo_flink(res->bo, &whandle->handle) == 0;
- case WINSYS_HANDLE_TYPE_KMS:
- whandle->handle = iris_bo_export_gem_handle(res->bo);
+ return iris_bo_flink(bo, &whandle->handle) == 0;
+ case WINSYS_HANDLE_TYPE_KMS: {
+ /* Because we share the same drm file across multiple iris_screen, when
+ * we export a GEM handle we must make sure it is valid in the DRM file
+ * descriptor the caller is using (this is the FD given at screen
+ * creation).
+ */
+ uint32_t handle;
+ if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
+ return false;
+ whandle->handle = handle;
return true;
+ }
case WINSYS_HANDLE_TYPE_FD:
- return iris_bo_export_dmabuf(res->bo, (int *) &whandle->handle) == 0;
+ return iris_bo_export_dmabuf(bo, (int *) &whandle->handle) == 0;
}
return false;
if (resource->target != PIPE_BUFFER)
return;
+ /* If it's already invalidated, don't bother doing anything. */
+ if (res->valid_buffer_range.start > res->valid_buffer_range.end)
+ return;
+
if (!resource_is_busy(ice, res)) {
/* The resource is idle, so just mark that it contains no data and
* keep using the same underlying buffer object.
/* Rebind the buffer, replacing any state referring to the old BO's
* address, and marking state dirty so it's reemitted.
*/
- ice->vtbl.rebind_buffer(ice, res, old_bo->gtt_offset);
+ screen->vtbl.rebind_buffer(ice, res);
util_range_set_empty(&res->valid_buffer_range);
.nr_samples = xfer->resource->nr_samples,
.nr_storage_samples = xfer->resource->nr_storage_samples,
.array_size = box->depth,
+ .format = res->internal_format,
};
if (xfer->resource->target == PIPE_BUFFER)
else
templ.target = PIPE_TEXTURE_2D;
- /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use
- * xfer->resource->format directly. Pick a bpb compatible format so
- * resource creation will succeed; blorp_copy will override it anyway.
- */
- switch (util_format_get_blocksizebits(res->internal_format)) {
- case 8: templ.format = PIPE_FORMAT_R8_UINT; break;
- case 16: templ.format = PIPE_FORMAT_R8G8_UINT; break;
- case 24: templ.format = PIPE_FORMAT_R8G8B8_UINT; break;
- case 32: templ.format = PIPE_FORMAT_R8G8B8A8_UINT; break;
- case 48: templ.format = PIPE_FORMAT_R16G16B16_UINT; break;
- case 64: templ.format = PIPE_FORMAT_R16G16B16A16_UINT; break;
- case 96: templ.format = PIPE_FORMAT_R32G32B32_UINT; break;
- case 128: templ.format = PIPE_FORMAT_R32G32B32A32_UINT; break;
- default: unreachable("Invalid bpb");
- }
-
map->staging = iris_resource_create(pscreen, &templ);
assert(map->staging);
}
}
+/**
+ * This function computes the tile_w (in bytes) and tile_h (in rows) of
+ * different tiling patterns.
+ */
+static void
+iris_resource_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
+ uint32_t *tile_w, uint32_t *tile_h)
+{
+ switch (tiling) {
+ case ISL_TILING_X:
+ *tile_w = 512;
+ *tile_h = 8;
+ break;
+ case ISL_TILING_Y0:
+ *tile_w = 128;
+ *tile_h = 32;
+ break;
+ case ISL_TILING_LINEAR:
+ *tile_w = cpp;
+ *tile_h = 1;
+ break;
+ default:
+ unreachable("not reached");
+ }
+
+}
+
+/**
+ * This function computes masks that may be used to select the bits of the X
+ * and Y coordinates that indicate the offset within a tile. If the BO is
+ * untiled, the masks are set to 0.
+ */
+static void
+iris_resource_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
+ uint32_t *mask_x, uint32_t *mask_y)
+{
+ uint32_t tile_w_bytes, tile_h;
+
+ iris_resource_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
+
+ *mask_x = tile_w_bytes / cpp - 1;
+ *mask_y = tile_h - 1;
+}
+
+/**
+ * Compute the offset (in bytes) from the start of the BO to the given x
+ * and y coordinate. For tiled BOs, caller must ensure that x and y are
+ * multiples of the tile size.
+ */
+static uint32_t
+iris_resource_get_aligned_offset(const struct iris_resource *res,
+ uint32_t x, uint32_t y)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
+ unsigned cpp = fmtl->bpb / 8;
+ uint32_t pitch = res->surf.row_pitch_B;
+
+ switch (res->surf.tiling) {
+ default:
+ unreachable("not reached");
+ case ISL_TILING_LINEAR:
+ return y * pitch + x * cpp;
+ case ISL_TILING_X:
+ assert((x % (512 / cpp)) == 0);
+ assert((y % 8) == 0);
+ return y * pitch + x / (512 / cpp) * 4096;
+ case ISL_TILING_Y0:
+ assert((x % (128 / cpp)) == 0);
+ assert((y % 32) == 0);
+ return y * pitch + x / (128 / cpp) * 4096;
+ }
+}
+
+/**
+ * Rendering with tiled buffers requires that the base address of the buffer
+ * be aligned to a page boundary. For renderbuffers, and sometimes with
+ * textures, we may want the surface to point at a texture image level that
+ * isn't at a page boundary.
+ *
+ * This function returns an appropriately-aligned base offset
+ * according to the tiling restrictions, plus any required x/y offset
+ * from there.
+ */
+uint32_t
+iris_resource_get_tile_offsets(const struct iris_resource *res,
+ uint32_t level, uint32_t z,
+ uint32_t *tile_x, uint32_t *tile_y)
+{
+ uint32_t x, y;
+ uint32_t mask_x, mask_y;
+
+ const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
+ const unsigned cpp = fmtl->bpb / 8;
+
+ iris_resource_get_tile_masks(res->surf.tiling, cpp, &mask_x, &mask_y);
+ get_image_offset_el(&res->surf, level, z, &x, &y);
+
+ *tile_x = x & mask_x;
+ *tile_y = y & mask_y;
+
+ return iris_resource_get_aligned_offset(res, x & ~mask_x, y & ~mask_y);
+}
+
/**
* Get pointer offset into stencil buffer.
*
* mesa: Fix return type of _mesa_get_format_bytes() (#37351)
*/
static intptr_t
-s8_offset(uint32_t stride, uint32_t x, uint32_t y, bool swizzled)
+s8_offset(uint32_t stride, uint32_t x, uint32_t y)
{
uint32_t tile_size = 4096;
uint32_t tile_width = 64;
+ 2 * (byte_y % 2)
+ 1 * (byte_x % 2);
- if (swizzled) {
- /* adjust for bit6 swizzling */
- if (((byte_x / 8) % 2) == 1) {
- if (((byte_y / 8) % 2) == 0) {
- u += 64;
- } else {
- u -= 64;
- }
- }
- }
-
return u;
}
const struct pipe_box *box = &xfer->box;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
struct isl_surf *surf = &res->surf;
- const bool has_swizzling = false;
if (xfer->usage & PIPE_TRANSFER_WRITE) {
uint8_t *untiled_s8_map = map->ptr;
for (uint32_t x = 0; x < box->width; x++) {
ptrdiff_t offset = s8_offset(surf->row_pitch_B,
x0_el + box->x + x,
- y0_el + box->y + y,
- has_swizzling);
+ y0_el + box->y + y);
tiled_s8_map[offset] =
untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x];
}
map->buffer = map->ptr = malloc(xfer->layer_stride * box->depth);
assert(map->buffer);
- const bool has_swizzling = false;
-
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
* invalidate is set, since we'll be writing the whole rectangle from our
for (uint32_t x = 0; x < box->width; x++) {
ptrdiff_t offset = s8_offset(surf->row_pitch_B,
x0_el + box->x + x,
- y0_el + box->y + y,
- has_swizzling);
+ y0_el + box->y + y);
untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x] =
tiled_s8_map[offset];
}
const bool has_swizzling = false;
- // XXX: PIPE_TRANSFER_READ?
if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
char *src =
iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
struct iris_resource *res = (struct iris_resource *)resource;
struct isl_surf *surf = &res->surf;
+ if (iris_resource_unfinished_aux_import(res))
+ iris_resource_finish_aux_import(ctx->screen, res);
+
if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
/* Replace the backing storage with a fresh buffer for non-async maps */
if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
usage |= PIPE_TRANSFER_DISCARD_RANGE;
}
- bool map_would_stall = false;
-
- if (resource->target != PIPE_BUFFER) {
- iris_resource_access_raw(ice, &ice->batches[IRIS_BATCH_RENDER], res,
- level, box->z, box->depth,
- usage & PIPE_TRANSFER_WRITE);
- }
-
if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
can_promote_to_async(res, box, usage)) {
usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
}
+ bool need_resolve = false;
+ bool need_color_resolve = false;
+
+ if (resource->target != PIPE_BUFFER) {
+ bool need_hiz_resolve = iris_resource_level_has_hiz(res, level);
+ bool need_stencil_resolve = res->aux.usage == ISL_AUX_USAGE_STC_CCS;
+
+ need_color_resolve =
+ (res->aux.usage == ISL_AUX_USAGE_CCS_D ||
+ res->aux.usage == ISL_AUX_USAGE_CCS_E ||
+ res->aux.usage == ISL_AUX_USAGE_GEN12_CCS_E) &&
+ iris_has_invalid_primary(res, level, 1, box->z, box->depth);
+
+ need_resolve = need_color_resolve ||
+ need_hiz_resolve ||
+ need_stencil_resolve;
+ }
+
+ bool map_would_stall = false;
+
if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
- map_would_stall = resource_is_busy(ice, res);
+ map_would_stall = need_resolve || resource_is_busy(ice, res);
if (map_would_stall && (usage & PIPE_TRANSFER_DONTBLOCK) &&
(usage & PIPE_TRANSFER_MAP_DIRECTLY))
xfer->box = *box;
*ptransfer = xfer;
+ map->dest_had_defined_contents =
+ util_ranges_intersect(&res->valid_buffer_range, box->x,
+ box->x + box->width);
+
if (usage & PIPE_TRANSFER_WRITE)
- util_range_add(&res->valid_buffer_range, box->x, box->x + box->width);
+ util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
/* Avoid using GPU copies for persistent/coherent buffers, as the idea
* there is to access them simultaneously on the CPU & GPU. This also
* temporary and map that, to avoid the resolve. (It might be better to
* a tiled temporary and use the tiled_memcpy paths...)
*/
- if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) &&
+ if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) && !need_color_resolve)
+ no_gpu = true;
+
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
+ if (fmtl->txc == ISL_TXC_ASTC)
+ no_gpu = true;
+
+ if (!map_would_stall &&
res->aux.usage != ISL_AUX_USAGE_CCS_E &&
- res->aux.usage != ISL_AUX_USAGE_CCS_D) {
+ res->aux.usage != ISL_AUX_USAGE_GEN12_CCS_E) {
no_gpu = true;
}
- if ((map_would_stall || res->aux.usage == ISL_AUX_USAGE_CCS_E) && !no_gpu) {
- /* If we need a synchronous mapping and the resource is busy,
- * we copy to/from a linear temporary buffer using the GPU.
+ if (!no_gpu) {
+ /* If we need a synchronous mapping and the resource is busy, or needs
+ * resolving, we copy to/from a linear temporary buffer using the GPU.
*/
map->batch = &ice->batches[IRIS_BATCH_RENDER];
map->blorp = &ice->blorp;
iris_map_copy_region(map);
} else {
- /* Otherwise we're free to map on the CPU. Flush if needed. */
+ /* Otherwise we're free to map on the CPU. */
+
+ if (need_resolve) {
+ iris_resource_access_raw(ice, res, level, box->z, box->depth,
+ usage & PIPE_TRANSFER_WRITE);
+ }
+
if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
if (iris_batch_references(&ice->batches[i], res->bo))
if (map->staging)
iris_flush_staging_region(xfer, box);
- for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
- if (ice->batches[i].contains_draw ||
- ice->batches[i].cache.render->entries) {
- iris_batch_maybe_flush(&ice->batches[i], 24);
- iris_flush_and_dirty_for_history(ice, &ice->batches[i], res,
- "cache history: transfer flush");
+ uint32_t history_flush = 0;
+
+ if (res->base.target == PIPE_BUFFER) {
+ if (map->staging)
+ history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
+
+ if (map->dest_had_defined_contents)
+ history_flush |= iris_flush_bits_for_history(res);
+
+ util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
+ }
+
+ if (history_flush & ~PIPE_CONTROL_CS_STALL) {
+ for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
+ struct iris_batch *batch = &ice->batches[i];
+ if (batch->contains_draw || batch->cache.render->entries) {
+ iris_batch_maybe_flush(batch, 24);
+ iris_emit_pipe_control_flush(batch,
+ "cache history: transfer flush",
+ history_flush);
+ }
}
}
struct iris_context *ice = (struct iris_context *)ctx;
struct iris_transfer *map = (void *) xfer;
- if (!(xfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT)) {
+ if (!(xfer->usage & (PIPE_TRANSFER_FLUSH_EXPLICIT |
+ PIPE_TRANSFER_COHERENT))) {
struct pipe_box flush_box = {
.x = 0, .y = 0, .z = 0,
.width = xfer->box.width,
slab_free(&ice->transfer_pool, map);
}
+/**
+ * The pipe->texture_subdata() driver hook.
+ *
+ * Mesa's state tracker takes this path whenever possible, even with
+ * PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER set.
+ */
+static void
+iris_texture_subdata(struct pipe_context *ctx,
+ struct pipe_resource *resource,
+ unsigned level,
+ unsigned usage,
+ const struct pipe_box *box,
+ const void *data,
+ unsigned stride,
+ unsigned layer_stride)
+{
+ struct iris_context *ice = (struct iris_context *)ctx;
+ struct iris_resource *res = (struct iris_resource *)resource;
+ const struct isl_surf *surf = &res->surf;
+
+ assert(resource->target != PIPE_BUFFER);
+
+ if (iris_resource_unfinished_aux_import(res))
+ iris_resource_finish_aux_import(ctx->screen, res);
+
+ /* Just use the transfer-based path for linear buffers - it will already
+ * do a direct mapping, or a simple linear staging buffer.
+ *
+ * Linear staging buffers appear to be better than tiled ones, too, so
+ * take that path if we need the GPU to perform color compression, or
+ * stall-avoidance blits.
+ */
+ if (surf->tiling == ISL_TILING_LINEAR ||
+ (isl_aux_usage_has_ccs(res->aux.usage) &&
+ res->aux.usage != ISL_AUX_USAGE_CCS_D) ||
+ resource_is_busy(ice, res)) {
+ return u_default_texture_subdata(ctx, resource, level, usage, box,
+ data, stride, layer_stride);
+ }
+
+ /* No state trackers pass any flags other than PIPE_TRANSFER_WRITE */
+
+ iris_resource_access_raw(ice, res, level, box->z, box->depth, true);
+
+ for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
+ if (iris_batch_references(&ice->batches[i], res->bo))
+ iris_batch_flush(&ice->batches[i]);
+ }
+
+ uint8_t *dst = iris_bo_map(&ice->dbg, res->bo, MAP_WRITE | MAP_RAW);
+
+ for (int s = 0; s < box->depth; s++) {
+ const uint8_t *src = data + s * layer_stride;
+
+ if (surf->tiling == ISL_TILING_W) {
+ unsigned x0_el, y0_el;
+ get_image_offset_el(surf, level, box->z + s, &x0_el, &y0_el);
+
+ for (unsigned y = 0; y < box->height; y++) {
+ for (unsigned x = 0; x < box->width; x++) {
+ ptrdiff_t offset = s8_offset(surf->row_pitch_B,
+ x0_el + box->x + x,
+ y0_el + box->y + y);
+ dst[offset] = src[y * stride + x];
+ }
+ }
+ } else {
+ unsigned x1, x2, y1, y2;
+
+ tile_extents(surf, box, level, s, &x1, &x2, &y1, &y2);
+
+ isl_memcpy_linear_to_tiled(x1, x2, y1, y2,
+ (void *)dst, (void *)src,
+ surf->row_pitch_B, stride,
+ false, surf->tiling, ISL_MEMCPY);
+ }
+ }
+}
+
/**
* Mark state dirty that needs to be re-emitted when a resource is written.
*/
iris_dirty_for_history(struct iris_context *ice,
struct iris_resource *res)
{
- uint64_t dirty = 0ull;
+ uint64_t stage_dirty = 0ull;
if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
- dirty |= IRIS_DIRTY_CONSTANTS_VS |
- IRIS_DIRTY_CONSTANTS_TCS |
- IRIS_DIRTY_CONSTANTS_TES |
- IRIS_DIRTY_CONSTANTS_GS |
- IRIS_DIRTY_CONSTANTS_FS |
- IRIS_DIRTY_CONSTANTS_CS |
- IRIS_ALL_DIRTY_BINDINGS;
+ stage_dirty |= ((uint64_t)res->bind_stages)
+ << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS;
}
- ice->state.dirty |= dirty;
+ ice->state.stage_dirty |= stage_dirty;
}
/**
iris_flush_and_dirty_for_history(struct iris_context *ice,
struct iris_batch *batch,
struct iris_resource *res,
+ uint32_t extra_flags,
const char *reason)
{
if (res->base.target != PIPE_BUFFER)
return;
- uint32_t flush = iris_flush_bits_for_history(res);
-
- /* We've likely used the rendering engine (i.e. BLORP) to write to this
- * surface. Flush the render cache so the data actually lands.
- */
- if (batch->name != IRIS_BATCH_COMPUTE)
- flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
+ uint32_t flush = iris_flush_bits_for_history(res) | extra_flags;
iris_emit_pipe_control_flush(batch, reason, flush);
pscreen->resource_from_user_memory = iris_resource_from_user_memory;
pscreen->resource_from_handle = iris_resource_from_handle;
pscreen->resource_get_handle = iris_resource_get_handle;
+ pscreen->resource_get_param = iris_resource_get_param;
pscreen->resource_destroy = u_transfer_helper_resource_destroy;
pscreen->transfer_helper =
u_transfer_helper_create(&transfer_vtbl, true, true, false, true);
ctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
ctx->transfer_unmap = u_transfer_helper_transfer_unmap;
ctx->buffer_subdata = u_default_buffer_subdata;
- ctx->texture_subdata = u_default_texture_subdata;
+ ctx->texture_subdata = iris_texture_subdata;
}
projects / mesa.git / blobdiff