nv50/ir: add nv50_ir_prog_info_out

[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_driver.h

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 72b9b1c7b2093edbff66770d187ae3db7a0b89ba..09079a4fb82bfd3c6e6988cdf28f238d7de4e3ce 100644 (file)
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -79,6 +79,9 @@ struct nv50_ir_prog_symbol
 #define NVISA_GM200_CHIPSET    0x120
 #define NVISA_GV100_CHIPSET    0x140
 
+struct nv50_ir_prog_info_out;
+
+/* used for the input data and assignSlot interface */
 struct nv50_ir_prog_info
 {
    uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
@@ -89,6 +92,51 @@ struct nv50_ir_prog_info
    uint8_t dbgFlags;
    bool omitLineNum; /* only used for printing the prog when dbgFlags is set */
 
+   struct {
+      uint32_t smemSize;  /* required shared memory per block */
+      uint8_t sourceRep;  /* PIPE_SHADER_IR_* */
+      const void *source;
+   } bin;
+
+   union {
+      struct {
+         uint32_t inputOffset; /* base address for user args */
+         uint32_t gridInfoBase;  /* base address for NTID,NCTAID */
+         uint16_t numThreads[3]; /* max number of threads */
+      } cp;
+   } prop;
+
+   struct {
+      int8_t genUserClip;        /* request user clip planes for ClipVertex */
+      uint8_t auxCBSlot;         /* driver constant buffer slot */
+      uint16_t ucpBase;          /* base address for UCPs */
+      uint16_t drawInfoBase;     /* base address for draw parameters */
+      uint16_t alphaRefBase;     /* base address for alpha test values */
+      int8_t viewportId;         /* output index of ViewportIndex */
+      bool mul_zero_wins;        /* program wants for x*0 = 0 */
+      bool nv50styleSurfaces;    /* generate gX[] access for raw buffers */
+      uint16_t texBindBase;      /* base address for tex handles (nve4) */
+      uint16_t fbtexBindBase;    /* base address for fbtex handle (nve4) */
+      uint16_t suInfoBase;       /* base address for surface info (nve4) */
+      uint16_t bindlessBase;     /* base address for bindless image info (nve4) */
+      uint16_t bufInfoBase;      /* base address for buffer info */
+      uint16_t sampleInfoBase;   /* base address for sample positions */
+      uint8_t msInfoCBSlot;      /* cX[] used for multisample info */
+      uint16_t msInfoBase;       /* base address for multisample info */
+      uint16_t uboInfoBase;      /* base address for compute UBOs (gk104+) */
+   } io;
+
+   /* driver callback to assign input/output locations */
+   int (*assignSlots)(struct nv50_ir_prog_info_out *);
+};
+
+/* the produced binary with metadata */
+struct nv50_ir_prog_info_out
+{
+   uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
+
+   uint8_t type; /* PIPE_SHADER */
+
    struct {
       int16_t maxGPR;     /* may be -1 if none used */
       uint32_t tlsSpace;  /* required local memory per thread */
@@ -96,8 +144,6 @@ struct nv50_ir_prog_info
       uint32_t *code;
       uint32_t codeSize;
       uint32_t instructions;
-      uint8_t sourceRep;  /* PIPE_SHADER_IR_* */
-      const void *source;
       void *relocData;
       void *fixupData;
    } bin;
@@ -131,54 +177,30 @@ struct nv50_ir_prog_info
          bool writesDepth;
          bool earlyFragTests;
          bool postDepthCoverage;
-         bool separateFragData;
          bool usesDiscard;
          bool usesSampleMaskIn;
          bool readsFramebuffer;
          bool readsSampleLocations;
+         bool separateFragData;
       } fp;
-      struct {
-         uint32_t inputOffset; /* base address for user args */
-         uint32_t gridInfoBase;  /* base address for NTID,NCTAID */
-         uint16_t numThreads[3]; /* max number of threads */
-      } cp;
    } prop;
 
-   uint8_t numBarriers;
-
    struct {
       uint8_t clipDistances;     /* number of clip distance outputs */
       uint8_t cullDistances;     /* number of cull distance outputs */
       int8_t genUserClip;        /* request user clip planes for ClipVertex */
-      uint8_t auxCBSlot;         /* driver constant buffer slot */
-      uint16_t ucpBase;          /* base address for UCPs */
-      uint16_t drawInfoBase;     /* base address for draw parameters */
-      uint16_t alphaRefBase;     /* base address for alpha test values */
       uint8_t instanceId;        /* system value index of InstanceID */
       uint8_t vertexId;          /* system value index of VertexID */
       uint8_t edgeFlagIn;
       uint8_t edgeFlagOut;
-      int8_t viewportId;         /* output index of ViewportIndex */
       uint8_t fragDepth;         /* output index of FragDepth */
       uint8_t sampleMask;        /* output index of SampleMask */
       uint8_t globalAccess;      /* 1 for read, 2 for wr, 3 for rw */
       bool fp64;                 /* program uses fp64 math */
-      bool mul_zero_wins;        /* program wants for x*0 = 0 */
       bool layer_viewport_relative;
-      bool nv50styleSurfaces;    /* generate gX[] access for raw buffers */
-      uint16_t texBindBase;      /* base address for tex handles (nve4) */
-      uint16_t fbtexBindBase;    /* base address for fbtex handle (nve4) */
-      uint16_t suInfoBase;       /* base address for surface info (nve4) */
-      uint16_t bindlessBase;     /* base address for bindless image info (nve4) */
-      uint16_t bufInfoBase;      /* base address for buffer info */
-      uint16_t sampleInfoBase;   /* base address for sample positions */
-      uint8_t msInfoCBSlot;      /* cX[] used for multisample info */
-      uint16_t msInfoBase;       /* base address for multisample info */
-      uint16_t uboInfoBase;      /* base address for compute UBOs (gk104+) */
    } io;
 
-   /* driver callback to assign input/output locations */
-   int (*assignSlots)(struct nv50_ir_prog_info *);
+   uint8_t numBarriers;
 
    void *driverPriv;
 };
@@ -190,7 +212,8 @@ extern "C" {
 const struct nir_shader_compiler_options *
 nv50_ir_nir_shader_compiler_options(int chipset);
 
-extern int nv50_ir_generate_code(struct nv50_ir_prog_info *);
+extern int nv50_ir_generate_code(struct nv50_ir_prog_info *,
+                                 struct nv50_ir_prog_info_out *);
 
 extern void nv50_ir_relocate_code(void *relocData, uint32_t *code,
                                   uint32_t codePos,