nvc0/ir: Properly lower 64-bit shifts when the shift value is >32

[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_lowering_nvc0.cpp

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 7243b1d2e41e839a27ef64d2d8be056aafa76797..6b51b7607cbd5c96619756e09f6c8000badd0c26 100644 (file)
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -216,7 +216,7 @@ NVC0LegalizeSSA::handleShift(Instruction *lo)
       // Compute LO (all shift values)
       bld.mkOp2(op, type, (dst[0] = bld.getSSA()), src[0], shift);
       // Compute HI (shift > 32)
-      bld.mkOp2(op, type, (hi2 = bld.getSSA()), src[1],
+      bld.mkOp2(op, type, (hi2 = bld.getSSA()), src[0],
                 bld.mkOp1v(OP_NEG, TYPE_S32, bld.getSSA(), x32_minus_shift))
          ->setPredicate(CC_NOT_P, pred);
       bld.mkOp2(OP_UNION, TYPE_U32, (dst[1] = bld.getSSA()), hi1, hi2);