nv50/ir: Add nv50_ir_prog_info serialize

[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_serialize.cpp

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
index 41f151ac28397a0f43892d4c1c8fcedee9dd634b..682a2014a749283acccf85882601c9ec01574ee4 100644 (file)
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
@@ -18,6 +18,45 @@ enum FixupApplyFunc {
    FLIP_GV100,
 };
 
+extern bool
+nv50_ir_prog_info_serialize(struct blob *blob, struct nv50_ir_prog_info *info)
+{
+   blob_write_uint32(blob, info->bin.smemSize);
+   blob_write_uint16(blob, info->target);
+   blob_write_uint8(blob, info->type);
+   blob_write_uint8(blob, info->optLevel);
+   blob_write_uint8(blob, info->dbgFlags);
+   blob_write_uint8(blob, info->omitLineNum);
+   blob_write_uint8(blob, info->bin.sourceRep);
+
+   switch(info->bin.sourceRep) {
+      case PIPE_SHADER_IR_TGSI: {
+         struct tgsi_token *tokens = (struct tgsi_token *)info->bin.source;
+         unsigned int num_tokens = tgsi_num_tokens(tokens);
+
+         blob_write_uint32(blob, num_tokens);
+         blob_write_bytes(blob, tokens, num_tokens * sizeof(struct tgsi_token));
+         break;
+      }
+      case PIPE_SHADER_IR_NIR: {
+         struct nir_shader *nir = (struct nir_shader *)info->bin.source;
+         nir_serialize(blob, nir, true);
+         break;
+      }
+      default:
+         ERROR("unhandled info->bin.sourceRep switch case\n");
+         assert(false);
+         return false;
+   }
+
+   if (info->type == PIPE_SHADER_COMPUTE)
+      blob_write_bytes(blob, &info->prop.cp, sizeof(info->prop.cp));
+
+   blob_write_bytes(blob, &info->io, sizeof(info->io));
+
+   return true;
+}
+
 extern bool
 nv50_ir_prog_info_out_serialize(struct blob *blob,
                                 struct nv50_ir_prog_info_out *info_out)