#include "util/format/u_format_s3tc.h"
#include "util/u_screen.h"
#include "pipe/p_screen.h"
-#include "compiler/nir/nir.h"
#include "nouveau_vp3_video.h"
+#include "codegen/nv50_ir_driver.h"
+
#include "nvc0/nvc0_context.h"
#include "nvc0/nvc0_screen.h"
#include "nvc0/mme/com9097.mme.h"
#include "nvc0/mme/com90c0.mme.h"
+#include "nvc0/mme/comc597.mme.h"
#include "nv50/g80_texture.xml.h"
if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
return false;
- /* Short-circuit the rest of the logic -- this is used by the state tracker
+ /* Short-circuit the rest of the logic -- this is used by the gallium frontend
* to determine valid MS levels in a no-attachments scenario.
*/
if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_PRIMITIVE_RESTART:
+ case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
return class_3d >= GP100_3D_CLASS;
/* caps has to be turned on with nir */
+ case PIPE_CAP_GL_SPIRV:
+ case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
case PIPE_CAP_INT64_DIVMOD:
return screen->prefer_nir ? 1 : 0;
+ /* nir related caps */
+ case PIPE_CAP_NIR_IMAGES_AS_DEREF:
+ return 0;
+
/* unsupported caps */
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: /* could be done */
case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
case PIPE_CAP_FRONTEND_NOOP:
- case PIPE_CAP_GL_SPIRV:
case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
case PIPE_CAP_PSIZ_CLAMPED:
case PIPE_SHADER_CAP_PREFERRED_IR:
return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
- uint32_t irs = 1 << PIPE_SHADER_IR_TGSI |
- 1 << PIPE_SHADER_IR_NIR;
+ uint32_t irs = 1 << PIPE_SHADER_IR_NIR |
+ ((class_3d >= GV100_3D_CLASS) ? 0 : 1 << PIPE_SHADER_IR_TGSI);
if (screen->force_enable_cl)
irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
return irs;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return shader != PIPE_SHADER_FRAGMENT;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
+ /* HW doesn't support indirect addressing of fragment program inputs
+ * on Volta. The binary driver generates a function to handle every
+ * possible indirection, and indirectly calls the function to handle
+ * this instead.
+ */
+ if (class_3d >= GV100_3D_CLASS)
+ return shader != PIPE_SHADER_FRAGMENT;
+ return 1;
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_FP16:
+ case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+ case PIPE_SHADER_CAP_INT16:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
return 0;
return pos + size;
}
+static int
+tu102_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
+ unsigned size, const uint32_t *data)
+{
+ struct nouveau_pushbuf *push = screen->base.pushbuf;
+
+ size /= 4;
+
+ assert((pos + size) <= 0x800);
+
+ BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
+ PUSH_DATA (push, (m - 0x3800) / 8);
+ PUSH_DATA (push, pos);
+ BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
+ PUSH_DATA (push, pos);
+ PUSH_DATAp(push, data, size);
+
+ return pos + (size / 3);
+}
+
static void
nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
{
BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
PUSH_DATA (push, 0xff);
PUSH_DATA (push, 0xff);
- BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
- PUSH_DATA (push, 0x3f);
+ if (obj_class < GV100_3D_CLASS) {
+ BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
+ PUSH_DATA (push, 0x3f);
+ }
BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
PUSH_DATA (push, (3 << 16) | 3);
BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
PUSH_DATA (push, 3);
- BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
- PUSH_DATA (push, 0x3fffff);
+ if (obj_class < GV100_3D_CLASS) {
+ BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
+ PUSH_DATA (push, 0x3fffff);
+ }
BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
PUSH_DATA (push, 1);
BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
case 0x110:
case 0x120:
case 0x130:
+ case 0x140:
+ case 0x160:
return nve4_screen_compute_setup(screen, screen->base.pushbuf);
default:
return -1;
nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
/* update the code segment setup */
- BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, screen->text->offset);
- PUSH_DATA (push, screen->text->offset);
- if (screen->compute) {
- BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
+ if (screen->eng3d->oclass < GV100_3D_CLASS) {
+ BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->text->offset);
PUSH_DATA (push, screen->text->offset);
+ if (screen->compute) {
+ BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
+ PUSH_DATAh(push, screen->text->offset);
+ PUSH_DATA (push, screen->text->offset);
+ }
}
return 0;
IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
}
-static const nir_shader_compiler_options nir_options = {
- .lower_fdiv = false,
- .lower_ffma = false,
- .fuse_ffma = false, /* nir doesn't track mad vs fma */
- .lower_flrp32 = true,
- .lower_flrp64 = true,
- .lower_fpow = false,
- .lower_fsat = false,
- .lower_fsqrt = false, // TODO: only before gm200
- .lower_fmod = true,
- .lower_bitfield_extract = false,
- .lower_bitfield_extract_to_shifts = false,
- .lower_bitfield_insert = false,
- .lower_bitfield_insert_to_shifts = false,
- .lower_bitfield_reverse = false,
- .lower_bit_count = false,
- .lower_ifind_msb = false,
- .lower_find_lsb = false,
- .lower_uadd_carry = true, // TODO
- .lower_usub_borrow = true, // TODO
- .lower_mul_high = false,
- .lower_negate = false,
- .lower_sub = true,
- .lower_scmp = true, // TODO: not implemented yet
- .lower_idiv = true,
- .lower_isign = false, // TODO
- .fdot_replicates = false, // TODO
- .lower_ffloor = false, // TODO
- .lower_ffract = true,
- .lower_fceil = false, // TODO
- .lower_ldexp = true,
- .lower_pack_half_2x16 = true,
- .lower_pack_unorm_2x16 = true,
- .lower_pack_snorm_2x16 = true,
- .lower_pack_unorm_4x8 = true,
- .lower_pack_snorm_4x8 = true,
- .lower_unpack_half_2x16 = true,
- .lower_unpack_unorm_2x16 = true,
- .lower_unpack_snorm_2x16 = true,
- .lower_unpack_unorm_4x8 = true,
- .lower_unpack_snorm_4x8 = true,
- .lower_extract_byte = true,
- .lower_extract_word = true,
- .lower_all_io_to_temps = false,
- .vertex_id_zero_based = false,
- .lower_base_vertex = false,
- .lower_helper_invocation = false,
- .lower_cs_local_index_from_id = true,
- .lower_cs_local_id_from_index = false,
- .lower_device_index_to_zero = false, // TODO
- .lower_wpos_pntc = false, // TODO
- .lower_hadd = true, // TODO
- .lower_add_sat = true, // TODO
- .use_interpolated_input_intrinsics = true,
- .lower_mul_2x32_64 = true, // TODO
- .max_unroll_iterations = 32,
- .lower_int64_options = nir_lower_ufind_msb64|nir_lower_divmod64, // TODO
- .lower_doubles_options = nir_lower_dmod, // TODO
- .lower_to_scalar = true,
-};
-
static const void *
nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
enum pipe_shader_ir ir,
enum pipe_shader_type shader)
{
+ struct nvc0_screen *screen = nvc0_screen(pscreen);
if (ir == PIPE_SHADER_IR_NIR)
- return &nir_options;
+ return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset);
return NULL;
}
case 0x110:
case 0x120:
case 0x130:
+ case 0x140:
+ case 0x160:
break;
default:
return NULL;
screen->base.fence.emit = nvc0_screen_fence_emit;
screen->base.fence.update = nvc0_screen_fence_update;
+ if (dev->chipset < 0x140) {
+ ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
+ NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
+ if (ret)
+ FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
- ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
- NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
- if (ret)
- FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
-
- BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
- PUSH_DATA (push, screen->nvsw->handle);
+ BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
+ PUSH_DATA (push, screen->nvsw->handle);
+ }
switch (dev->chipset & ~0xf) {
+ case 0x160:
+ case 0x140:
case 0x130:
case 0x120:
case 0x110:
PUSH_DATA (push, screen->fence.bo->offset + 16);
switch (dev->chipset & ~0xf) {
+ case 0x160:
+ obj_class = TU102_3D_CLASS;
+ break;
+ case 0x140:
+ obj_class = GV100_3D_CLASS;
+ break;
case 0x130:
switch (dev->chipset) {
case 0x130:
PUSH_DATA (push, 16384 << 16);
}
+ if (screen->eng3d->oclass < TU102_3D_CLASS) {
#define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
- i = 0;
- MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
- MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
- MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
- MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
- MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
- MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
- MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
- MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
- MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
- MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
- MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
- MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
- MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
- MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
- MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
- MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
+ i = 0;
+ MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
+ MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
+ MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
+ MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
+ MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
+ MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
+ MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
+ MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
+ MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
+ MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
+ MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
+ MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
+ MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
+ MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
+ MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
+ MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
+ } else {
+#undef MK_MACRO
+#define MK_MACRO(m, n) i = tu102_graph_set_macro(screen, m, i, sizeof(n), n);
+
+ i = 0;
+ MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mmec597_per_instance_bf);
+ MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mmec597_blend_enables);
+ MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mmec597_vertex_array_select);
+ MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mmec597_tep_select);
+ MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mmec597_gp_select);
+ MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mmec597_poly_mode_front);
+ MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mmec597_poly_mode_back);
+ MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mmec597_draw_arrays_indirect);
+ MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mmec597_draw_elts_indirect);
+ MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mmec597_draw_arrays_indirect_count);
+ MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mmec597_draw_elts_indirect_count);
+ MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mmec597_query_buffer_write);
+ MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mmec597_conservative_raster_state);
+ MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mmec597_compute_counter);
+ MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mmec597_compute_counter_to_query);
+ }
BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
PUSH_DATA (push, 1);
projects / mesa.git / blobdiff