gallium: remove pipe_index_buffer and set_index_buffer

[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_vbo.c

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
index 7cea5fb692ef13ab764f398c7bf556e558cd35ec..86c5e8bf95546ef9cdb75ad64bf8115e054d8314 100644 (file)
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
@@ -522,26 +522,6 @@ nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
       nvc0_validate_vertex_buffers(nvc0);
 }
 
-void
-nvc0_idxbuf_validate(struct nvc0_context *nvc0)
-{
-   struct nouveau_pushbuf *push = nvc0->base.pushbuf;
-   struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer);
-
-   assert(buf);
-   assert(nouveau_resource_mapped_by_gpu(&buf->base));
-
-   PUSH_SPACE(push, 6);
-   BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5);
-   PUSH_DATAh(push, buf->address + nvc0->idxbuf.offset);
-   PUSH_DATA (push, buf->address + nvc0->idxbuf.offset);
-   PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
-   PUSH_DATA (push, buf->address + buf->base.width0 - 1);
-   PUSH_DATA (push, nvc0->idxbuf.index_size >> 1);
-
-   BCTX_REFN(nvc0->bufctx_3d, 3D_IDX, buf, RD);
-}
-
 #define NVC0_PRIM_GL_CASE(n) \
    case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 
@@ -588,7 +568,7 @@ nvc0_draw_arrays(struct nvc0_context *nvc0,
    unsigned prim;
 
    if (nvc0->state.index_bias) {
-      /* index_bias is implied 0 if !info->indexed (really ?) */
+      /* index_bias is implied 0 if !info->index_size (really ?) */
       /* TODO: can we deactivate it for the VERTEX_BUFFER_FIRST command ? */
       PUSH_SPACE(push, 2);
       IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
@@ -711,12 +691,13 @@ nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
 
 static void
 nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten,
+                   const struct pipe_draw_info *info,
                    unsigned mode, unsigned start, unsigned count,
-                   unsigned instance_count, int32_t index_bias)
+                   unsigned instance_count, int32_t index_bias,
+                  unsigned index_size)
 {
    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
    unsigned prim;
-   const unsigned index_size = nvc0->idxbuf.index_size;
 
    prim = nvc0_prim_gl(mode);
 
@@ -729,7 +710,7 @@ nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten,
       nvc0->state.index_bias = index_bias;
    }
 
-   if (nvc0->idxbuf.buffer) {
+   if (!info->has_user_indices) {
       PUSH_SPACE(push, 1);
       IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), prim);
       do {
@@ -745,7 +726,7 @@ nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten,
       } while (instance_count);
       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
    } else {
-      const void *data = nvc0->idxbuf.user_buffer;
+      const void *data = info->index.user;
 
       while (instance_count--) {
          PUSH_SPACE(push, 2);
@@ -841,9 +822,9 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
    BEGIN_NVC0(push, NVC0_3D(CB_POS), 1);
    PUSH_DATA (push, NVC0_CB_AUX_DRAW_INFO);
 
-   if (info->indexed) {
-      assert(nvc0->idxbuf.buffer);
-      assert(nouveau_resource_mapped_by_gpu(nvc0->idxbuf.buffer));
+   if (info->index_size) {
+      assert(!info->has_user_indices);
+      assert(nouveau_resource_mapped_by_gpu(info->index.resource));
       size = 5;
       if (buf_count)
          macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT;
@@ -851,7 +832,7 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
          macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT;
    } else {
       if (nvc0->state.index_bias) {
-         /* index_bias is implied 0 if !info->indexed (really ?) */
+         /* index_bias is implied 0 if !info->index_size (really ?) */
          IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
          IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
          nvc0->state.index_bias = 0;
@@ -940,6 +921,9 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
    struct nvc0_screen *screen = nvc0->screen;
    int s;
 
+   if (info->index_size)
+      nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_IDX);
+
    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
    nvc0->vb_elt_first = info->min_index + info->index_bias;
    nvc0->vb_elt_limit = info->max_index - info->min_index;
@@ -950,7 +934,7 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
     * if index count is larger and we expect repeated vertices, suggest upload.
     */
    nvc0->vbo_push_hint =
-      !info->indirect && info->indexed &&
+      !info->indirect && info->index_size &&
       (nvc0->vb_elt_limit >= (info->count * 2));
 
    /* Check whether we want to switch vertex-submission mode. */
@@ -974,6 +958,23 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
       IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices);
    }
 
+   if (info->index_size && !info->has_user_indices) {
+      struct nv04_resource *buf = nv04_resource(info->index.resource);
+
+      assert(buf);
+      assert(nouveau_resource_mapped_by_gpu(&buf->base));
+
+      PUSH_SPACE(push, 6);
+      BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5);
+      PUSH_DATAh(push, buf->address);
+      PUSH_DATA (push, buf->address);
+      PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
+      PUSH_DATA (push, buf->address + buf->base.width0 - 1);
+      PUSH_DATA (push, info->index_size >> 1);
+
+      BCTX_REFN(nvc0->bufctx_3d, 3D_IDX, buf, RD);
+   }
+
    nvc0_state_validate_3d(nvc0, ~0);
 
    if (nvc0->vertprog->vp.need_draw_parameters && !info->indirect) {
@@ -1046,8 +1047,8 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 
    nvc0->base.vbo_dirty |= !!nvc0->vtxbufs_coherent;
 
-   if (!nvc0->base.vbo_dirty && nvc0->idxbuf.buffer &&
-       nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
+   if (!nvc0->base.vbo_dirty && info->index_size && !info->has_user_indices &&
+       info->index.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
       nvc0->base.vbo_dirty = true;
 
    nvc0_update_prim_restart(nvc0, info->primitive_restart, info->restart_index);
@@ -1064,15 +1065,15 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
    if (unlikely(info->count_from_stream_output)) {
       nvc0_draw_stream_output(nvc0, info);
    } else
-   if (info->indexed) {
+   if (info->index_size) {
       bool shorten = info->max_index <= 65535;
 
       if (info->primitive_restart && info->restart_index > 65535)
          shorten = false;
 
-      nvc0_draw_elements(nvc0, shorten,
+      nvc0_draw_elements(nvc0, shorten, info,
                          info->mode, info->start, info->count,
-                         info->instance_count, info->index_bias);
+                         info->instance_count, info->index_bias, info->index_size);
    } else {
       nvc0_draw_arrays(nvc0,
                        info->mode, info->start, info->count,