nouveau: Support X8R8G8B8 textures on nv30, nv40 and RTs on nv10-nv40.

[mesa.git] / src / gallium / drivers / nv10 / nv10_state_emit.c

diff --git a/src/gallium/drivers/nv10/nv10_state_emit.c b/src/gallium/drivers/nv10/nv10_state_emit.c
index 18566986b064f582e3599e950c1b7237d5c41157..2577ab73b5672f064431246c970fc5118fd9cf3f 100644 (file)
--- a/src/gallium/drivers/nv10/nv10_state_emit.c
+++ b/src/gallium/drivers/nv10/nv10_state_emit.c
@@ -1,5 +1,3 @@
-#include "pipe/p_util.h"
-
 #include "nv10_context.h"
 #include "nv10_state.h"
 
@@ -63,29 +61,34 @@ static void nv10_state_emit_dsa(struct nv10_context* nv10)
 {
        struct nv10_depth_stencil_alpha_state *d = nv10->dsa;
 
-       BEGIN_RING(celsius, NV10TCL_DEPTH_FUNC, 3);
-       OUT_RINGp ((uint32_t *)&d->depth, 3);
+       BEGIN_RING(celsius, NV10TCL_DEPTH_FUNC, 1);
+       OUT_RING (d->depth.func);
+
+       BEGIN_RING(celsius, NV10TCL_DEPTH_WRITE_ENABLE, 1);
+       OUT_RING (d->depth.write_enable);
+
+       BEGIN_RING(celsius, NV10TCL_DEPTH_TEST_ENABLE, 1);
+       OUT_RING (d->depth.test_enable);
+
+#if 0
        BEGIN_RING(celsius, NV10TCL_STENCIL_ENABLE, 1);
        OUT_RING (d->stencil.enable);
        BEGIN_RING(celsius, NV10TCL_STENCIL_MASK, 7);
        OUT_RINGp ((uint32_t *)&(d->stencil.wmask), 7);
-       BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_ENABLE, 3);
-       OUT_RINGp ((uint32_t *)&d->alpha.enabled, 3);
+#endif
+
+       BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_ENABLE, 1);
+       OUT_RING (d->alpha.enabled);
+
+       BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_FUNC, 1);
+       OUT_RING (d->alpha.func);
+
+       BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_REF, 1);
+       OUT_RING (d->alpha.ref);
 }
 
 static void nv10_state_emit_viewport(struct nv10_context* nv10)
 {
-       struct pipe_viewport_state *vpt = nv10->viewport;
-
-/*     OUT_RINGf (vpt->translate[0]);
-       OUT_RINGf (vpt->translate[1]);
-       OUT_RINGf (vpt->translate[2]);
-       OUT_RINGf (vpt->translate[3]);*/
-       BEGIN_RING(celsius, NV10TCL_VIEWPORT_SCALE_X, 4);
-       OUT_RINGf (vpt->scale[0]);
-       OUT_RINGf (vpt->scale[1]);
-       OUT_RINGf (vpt->scale[2]);
-       OUT_RINGf (vpt->scale[3]);
 }
 
 static void nv10_state_emit_scissor(struct nv10_context* nv10)
@@ -100,14 +103,15 @@ static void nv10_state_emit_scissor(struct nv10_context* nv10)
 static void nv10_state_emit_framebuffer(struct nv10_context* nv10)
 {
        struct pipe_framebuffer_state* fb = nv10->framebuffer;
-       struct pipe_surface *rt, *zeta;
+       struct nv04_surface *rt, *zeta = NULL;
        uint32_t rt_format, w, h;
        int colour_format = 0, zeta_format = 0;
+        struct nv10_miptree *nv10mt = 0;
 
        w = fb->cbufs[0]->width;
        h = fb->cbufs[0]->height;
        colour_format = fb->cbufs[0]->format;
-       rt = fb->cbufs[0];
+       rt = (struct nv04_surface *)fb->cbufs[0];
 
        if (fb->zsbuf) {
                if (colour_format) {
@@ -119,12 +123,15 @@ static void nv10_state_emit_framebuffer(struct nv10_context* nv10)
                }
 
                zeta_format = fb->zsbuf->format;
-               zeta = fb->zsbuf;
+               zeta = (struct nv04_surface *)fb->zsbuf;
        }
 
        rt_format = NV10TCL_RT_FORMAT_TYPE_LINEAR;
 
        switch (colour_format) {
+       case PIPE_FORMAT_X8R8G8B8_UNORM:
+               rt_format |= NV10TCL_RT_FORMAT_COLOR_X8R8G8B8;
+               break;
        case PIPE_FORMAT_A8R8G8B8_UNORM:
        case 0:
                rt_format |= NV10TCL_RT_FORMAT_COLOR_A8R8G8B8;
@@ -138,17 +145,19 @@ static void nv10_state_emit_framebuffer(struct nv10_context* nv10)
 
        if (zeta) {
                BEGIN_RING(celsius, NV10TCL_RT_PITCH, 1);
-               OUT_RING  ( (rt->pitch * rt->cpp) | ( (zeta->pitch * zeta->cpp) << 16) );
+               OUT_RING  (rt->pitch | (zeta->pitch << 16));
        } else {
                BEGIN_RING(celsius, NV10TCL_RT_PITCH, 1);
-               OUT_RING  ( (rt->pitch * rt->cpp) );
+               OUT_RING  (rt->pitch | (rt->pitch << 16));
        }
 
-       nv10->rt[0] = rt->buffer;
+       nv10mt = (struct nv10_miptree *)rt->base.texture;
+       nv10->rt[0] = nv10mt->buffer;
 
        if (zeta_format)
        {
-               nv10->zeta = zeta->buffer;
+               nv10mt = (struct nv10_miptree *)zeta->base.texture;
+               nv10->zeta = nv10mt->buffer;
        }
 
        BEGIN_RING(celsius, NV10TCL_RT_HORIZ, 3);
@@ -156,8 +165,8 @@ static void nv10_state_emit_framebuffer(struct nv10_context* nv10)
        OUT_RING  ((h << 16) | 0);
        OUT_RING  (rt_format);
        BEGIN_RING(celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 2);
-       OUT_RING  (((w - 1) << 16) | 0);
-       OUT_RING  (((h - 1) << 16) | 0);
+       OUT_RING  (((w - 1) << 16) | 0 | 0x08000800);
+       OUT_RING  (((h - 1) << 16) | 0 | 0x08000800);
 }
 
 static void nv10_vertex_layout(struct nv10_context *nv10)