(swz[2] << NV50_TIC_0_MAPB__SHIFT) |
(swz[3] << NV50_TIC_0_MAPA__SHIFT);
- /* tic[1] = mt->base.bo->offset; */
+ tic[1] = /* mt->base.bo->offset; */ 0;
tic[2] = /* mt->base.bo->offset >> 32 */ 0;
tic[2] |= 0x10001000 | /* NV50_TIC_2_NO_BORDER */ 0x40000000;
depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
+ if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY ||
+ mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) {
+ tic[1] = view->pipe.u.tex.first_layer * mt->layer_stride;
+ depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
+ }
+
switch (mt->base.base.target) {
case PIPE_TEXTURE_1D:
tic[2] |= NV50_TIC_2_TARGET_1D;
res = &nv50_miptree(tic->pipe.texture)->base;
if (tic->id < 0) {
+ uint32_t offset = tic->tic[1];
+
tic->id = nv50_screen_tic_alloc(nv50->screen, tic);
MARK_RING (chan, 24 + 8, 4);
OUT_RING (chan, 0);
BEGIN_RING_NI(chan, RING_2D(SIFC_DATA), 8);
OUT_RING (chan, tic->tic[0]);
- OUT_RELOCl(chan, res->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
- OUT_RELOC (chan, res->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
+ OUT_RELOCl(chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+ OUT_RELOC (chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
NOUVEAU_BO_HIGH | NOUVEAU_BO_OR, tic->tic[2], tic->tic[2]);
OUT_RINGp (chan, &tic->tic[3], 5);