-/* Lower csel with mixed condition channels to mulitple csel instructions. For
- * context, the csel ops on Midgard are vector in *outputs*, but not in
- * *conditions*. So, if the condition is e.g. yyyy, a single op can select a
- * vec4. But if the condition is e.g. xyzw, four ops are needed as the ISA
- * can't cope with the divergent channels.*/
-
-static void
-midgard_nir_lower_mixed_csel_body(nir_builder *b, nir_alu_instr *alu)
-{
- if (alu->op != nir_op_bcsel)
- return;
-
- b->cursor = nir_before_instr(&alu->instr);
-
- /* Must be run before registering */
- assert(alu->dest.dest.is_ssa);
-
- /* Check for mixed condition */
-
- unsigned comp = alu->src[0].swizzle[0];
- unsigned nr_components = alu->dest.dest.ssa.num_components;
-
- bool mixed = false;
-
- for (unsigned c = 1; c < nr_components; ++c)
- mixed |= (alu->src[0].swizzle[c] != comp);
-
- if (!mixed)
- return;
-
- /* We're mixed, so lower */
-
- assert(nr_components <= 4);
- nir_ssa_def *results[4];
-
- nir_ssa_def *cond = nir_ssa_for_alu_src(b, alu, 0);
- nir_ssa_def *choice0 = nir_ssa_for_alu_src(b, alu, 1);
- nir_ssa_def *choice1 = nir_ssa_for_alu_src(b, alu, 2);
-
- for (unsigned c = 0; c < nr_components; ++c) {
- results[c] = nir_bcsel(b,
- nir_channel(b, cond, c),
- nir_channel(b, choice0, c),
- nir_channel(b, choice1, c));
- }
-
- /* Replace with our scalarized version */
-
- nir_ssa_def *result = nir_vec(b, results, nr_components);
- nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(result));
-}
-