}
static unsigned
-panfrost_translate_compare_func(enum pipe_compare_func in)
+translate_tex_wrap(enum pipe_tex_wrap w)
{
- switch (in) {
- case PIPE_FUNC_NEVER:
- return MALI_FUNC_NEVER;
-
- case PIPE_FUNC_LESS:
- return MALI_FUNC_LESS;
-
- case PIPE_FUNC_EQUAL:
- return MALI_FUNC_EQUAL;
-
- case PIPE_FUNC_LEQUAL:
- return MALI_FUNC_LEQUAL;
-
- case PIPE_FUNC_GREATER:
- return MALI_FUNC_GREATER;
-
- case PIPE_FUNC_NOTEQUAL:
- return MALI_FUNC_NOT_EQUAL;
-
- case PIPE_FUNC_GEQUAL:
- return MALI_FUNC_GEQUAL;
-
- case PIPE_FUNC_ALWAYS:
- return MALI_FUNC_ALWAYS;
-
- default:
- unreachable("Invalid func");
+ switch (w) {
+ case PIPE_TEX_WRAP_REPEAT: return MALI_WRAP_MODE_REPEAT;
+ case PIPE_TEX_WRAP_CLAMP: return MALI_WRAP_MODE_CLAMP;
+ case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return MALI_WRAP_MODE_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return MALI_WRAP_MODE_CLAMP_TO_BORDER;
+ case PIPE_TEX_WRAP_MIRROR_REPEAT: return MALI_WRAP_MODE_MIRRORED_REPEAT;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP: return MALI_WRAP_MODE_MIRRORED_CLAMP;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER;
+ default: unreachable("Invalid wrap");
}
}
-static unsigned
-panfrost_translate_stencil_op(enum pipe_stencil_op in)
-{
- switch (in) {
- case PIPE_STENCIL_OP_KEEP:
- return MALI_STENCIL_OP_KEEP;
-
- case PIPE_STENCIL_OP_ZERO:
- return MALI_STENCIL_OP_ZERO;
-
- case PIPE_STENCIL_OP_REPLACE:
- return MALI_STENCIL_OP_REPLACE;
-
- case PIPE_STENCIL_OP_INCR:
- return MALI_STENCIL_OP_INCR_SAT;
-
- case PIPE_STENCIL_OP_DECR:
- return MALI_STENCIL_OP_DECR_SAT;
-
- case PIPE_STENCIL_OP_INCR_WRAP:
- return MALI_STENCIL_OP_INCR_WRAP;
+/* The hardware compares in the wrong order order, so we have to flip before
+ * encoding. Yes, really. */
- case PIPE_STENCIL_OP_DECR_WRAP:
- return MALI_STENCIL_OP_DECR_WRAP;
+static enum mali_func
+panfrost_sampler_compare_func(const struct pipe_sampler_state *cso)
+{
+ if (!cso->compare_mode)
+ return MALI_FUNC_NEVER;
- case PIPE_STENCIL_OP_INVERT:
- return MALI_STENCIL_OP_INVERT;
+ enum mali_func f = panfrost_translate_compare_func(cso->compare_func);
+ return panfrost_flip_compare_func(f);
+}
- default:
- unreachable("Invalid stencil op");
+static enum mali_mipmap_mode
+pan_pipe_to_mipmode(enum pipe_tex_mipfilter f)
+{
+ switch (f) {
+ case PIPE_TEX_MIPFILTER_NEAREST: return MALI_MIPMAP_MODE_NEAREST;
+ case PIPE_TEX_MIPFILTER_LINEAR: return MALI_MIPMAP_MODE_TRILINEAR;
+ case PIPE_TEX_MIPFILTER_NONE: return MALI_MIPMAP_MODE_NONE;
+ default: unreachable("Invalid");
}
}
-static unsigned
-translate_tex_wrap(enum pipe_tex_wrap w)
+void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso,
+ struct mali_midgard_sampler_packed *hw)
{
- switch (w) {
- case PIPE_TEX_WRAP_REPEAT:
- return MALI_WRAP_MODE_REPEAT;
-
- case PIPE_TEX_WRAP_CLAMP:
- return MALI_WRAP_MODE_CLAMP;
+ pan_pack(hw, MIDGARD_SAMPLER, cfg) {
+ cfg.magnify_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
+ cfg.minify_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
+ cfg.mipmap_mode = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR) ?
+ MALI_MIPMAP_MODE_TRILINEAR : MALI_MIPMAP_MODE_NEAREST;
+ cfg.normalized_coordinates = cso->normalized_coords;
- case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
- return MALI_WRAP_MODE_CLAMP_TO_EDGE;
+ cfg.lod_bias = FIXED_16(cso->lod_bias, true);
- case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
- return MALI_WRAP_MODE_CLAMP_TO_BORDER;
+ cfg.minimum_lod = FIXED_16(cso->min_lod, false);
- case PIPE_TEX_WRAP_MIRROR_REPEAT:
- return MALI_WRAP_MODE_MIRRORED_REPEAT;
+ /* If necessary, we disable mipmapping in the sampler descriptor by
+ * clamping the LOD as tight as possible (from 0 to epsilon,
+ * essentially -- remember these are fixed point numbers, so
+ * epsilon=1/256) */
- case PIPE_TEX_WRAP_MIRROR_CLAMP:
- return MALI_WRAP_MODE_MIRRORED_CLAMP;
+ cfg.maximum_lod = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) ?
+ cfg.minimum_lod + 1 :
+ FIXED_16(cso->max_lod, false);
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
- return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE;
+ cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s);
+ cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t);
+ cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r);
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
- return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER;
+ cfg.compare_function = panfrost_sampler_compare_func(cso);
+ cfg.seamless_cube_map = cso->seamless_cube_map;
- default:
- unreachable("Invalid wrap");
+ cfg.border_color_r = cso->border_color.f[0];
+ cfg.border_color_g = cso->border_color.f[1];
+ cfg.border_color_b = cso->border_color.f[2];
+ cfg.border_color_a = cso->border_color.f[3];
}
}
-void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso,
- struct mali_sampler_descriptor *hw)
-{
- unsigned func = panfrost_translate_compare_func(cso->compare_func);
- bool min_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
- bool mag_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
- bool mip_linear = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR;
- unsigned min_filter = min_nearest ? MALI_SAMP_MIN_NEAREST : 0;
- unsigned mag_filter = mag_nearest ? MALI_SAMP_MAG_NEAREST : 0;
- unsigned mip_filter = mip_linear ?
- (MALI_SAMP_MIP_LINEAR_1 | MALI_SAMP_MIP_LINEAR_2) : 0;
- unsigned normalized = cso->normalized_coords ? MALI_SAMP_NORM_COORDS : 0;
-
- *hw = (struct mali_sampler_descriptor) {
- .filter_mode = min_filter | mag_filter | mip_filter |
- normalized,
- .wrap_s = translate_tex_wrap(cso->wrap_s),
- .wrap_t = translate_tex_wrap(cso->wrap_t),
- .wrap_r = translate_tex_wrap(cso->wrap_r),
- .compare_func = cso->compare_mode ?
- panfrost_flip_compare_func(func) :
- MALI_FUNC_NEVER,
- .border_color = {
- cso->border_color.f[0],
- cso->border_color.f[1],
- cso->border_color.f[2],
- cso->border_color.f[3]
- },
- .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */
- .max_lod = FIXED_16(cso->max_lod, false),
- .lod_bias = FIXED_16(cso->lod_bias, true), /* can be negative */
- .seamless_cube_map = cso->seamless_cube_map,
- };
-
- /* If necessary, we disable mipmapping in the sampler descriptor by
- * clamping the LOD as tight as possible (from 0 to epsilon,
- * essentially -- remember these are fixed point numbers, so
- * epsilon=1/256) */
-
- if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
- hw->max_lod = hw->min_lod + 1;
-}
-
void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso,
- struct bifrost_sampler_descriptor *hw)
+ struct mali_bifrost_sampler_packed *hw)
{
- *hw = (struct bifrost_sampler_descriptor) {
- .unk1 = 0x1,
- .wrap_s = translate_tex_wrap(cso->wrap_s),
- .wrap_t = translate_tex_wrap(cso->wrap_t),
- .wrap_r = translate_tex_wrap(cso->wrap_r),
- .unk8 = 0x8,
- .min_filter = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST,
- .norm_coords = cso->normalized_coords,
- .mip_filter = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR,
- .mag_filter = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR,
- .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */
- .max_lod = FIXED_16(cso->max_lod, false),
- };
-
- /* If necessary, we disable mipmapping in the sampler descriptor by
- * clamping the LOD as tight as possible (from 0 to epsilon,
- * essentially -- remember these are fixed point numbers, so
- * epsilon=1/256) */
-
- if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
- hw->max_lod = hw->min_lod + 1;
-}
-
-static void
-panfrost_make_stencil_state(const struct pipe_stencil_state *in,
- void *out)
-{
- pan_pack(out, STENCIL, cfg) {
- cfg.mask = in->valuemask;
- cfg.compare_function = panfrost_translate_compare_func(in->func);
- cfg.stencil_fail = panfrost_translate_stencil_op(in->fail_op);
- cfg.depth_fail = panfrost_translate_stencil_op(in->zfail_op);
- cfg.depth_pass = panfrost_translate_stencil_op(in->zpass_op);
+ pan_pack(hw, BIFROST_SAMPLER, cfg) {
+ cfg.magnify_linear = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR;
+ cfg.minify_linear = cso->min_img_filter == PIPE_TEX_FILTER_LINEAR;
+ cfg.mipmap_mode = pan_pipe_to_mipmode(cso->min_mip_filter);
+ cfg.normalized_coordinates = cso->normalized_coords;
+
+ cfg.lod_bias = FIXED_16(cso->lod_bias, true);
+ cfg.minimum_lod = FIXED_16(cso->min_lod, false);
+ cfg.maximum_lod = FIXED_16(cso->max_lod, false);
+
+ cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s);
+ cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t);
+ cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r);
+
+ cfg.compare_function = panfrost_sampler_compare_func(cso);
+ cfg.seamless_cube_map = cso->seamless_cube_map;
}
}
panfrost_frag_meta_zsa_update(struct panfrost_context *ctx,
struct mali_shader_meta *fragmeta)
{
- const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil;
+ const struct panfrost_zsa_state *so = ctx->depth_stencil;
int zfunc = PIPE_FUNC_ALWAYS;
- if (!zsa) {
- struct pipe_stencil_state default_stencil = {
- .enabled = 0,
- .func = PIPE_FUNC_ALWAYS,
- .fail_op = PIPE_STENCIL_OP_KEEP,
- .zfail_op = PIPE_STENCIL_OP_KEEP,
- .zpass_op = PIPE_STENCIL_OP_KEEP,
- .writemask = 0xFF,
- .valuemask = 0xFF
- };
-
- panfrost_make_stencil_state(&default_stencil,
- &fragmeta->stencil_front);
- fragmeta->stencil_mask_front = default_stencil.writemask;
- fragmeta->stencil_back = fragmeta->stencil_front;
- fragmeta->stencil_mask_back = default_stencil.writemask;
+ if (!so) {
+ /* If stenciling is disabled, the state is irrelevant */
SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, false);
SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, false);
} else {
SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST,
- zsa->stencil[0].enabled);
- panfrost_make_stencil_state(&zsa->stencil[0],
- &fragmeta->stencil_front);
- fragmeta->stencil_mask_front = zsa->stencil[0].writemask;
+ so->base.stencil[0].enabled);
+
+ fragmeta->stencil_mask_front = so->stencil_mask_front;
+ fragmeta->stencil_mask_back = so->stencil_mask_back;
- /* Bottom 8-bits of stencil state is the stencil ref, ref is no
- * more than 8-bits. Be extra careful. */
- fragmeta->stencil_front.opaque[0] |= ctx->stencil_ref.ref_value[0];
+ /* Bottom bits for stencil ref, exactly one word */
+ fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0];
/* If back-stencil is not enabled, use the front values */
- if (zsa->stencil[1].enabled) {
- panfrost_make_stencil_state(&zsa->stencil[1],
- &fragmeta->stencil_back);
- fragmeta->stencil_mask_back = zsa->stencil[1].writemask;
- fragmeta->stencil_back.opaque[0] |= ctx->stencil_ref.ref_value[1];
- } else {
+ if (so->base.stencil[1].enabled)
+ fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1];
+ else
fragmeta->stencil_back = fragmeta->stencil_front;
- fragmeta->stencil_mask_back = fragmeta->stencil_mask_front;
- }
- if (zsa->depth.enabled)
- zfunc = zsa->depth.func;
+ if (so->base.depth.enabled)
+ zfunc = so->base.depth.func;
/* Depth state (TODO: Refactor) */
SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK,
- zsa->depth.writemask);
+ so->base.depth.writemask);
}
fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
bool msaa = ctx->rasterizer && ctx->rasterizer->base.multisample;
- fragmeta->coverage_mask = (msaa ? ctx->sample_mask : ~0) & 0xF;
+ fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0;
fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10;
fragmeta->unknown2_4 = 0x4e0;
* depends on if depth/stencil is used for the draw or not.
* Just one of depth OR stencil is enough to trigger this. */
- const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil;
+ const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base;
bool zs_enabled = fs->writes_depth || fs->writes_stencil;
if (zsa) {
return;
if (device->quirks & IS_BIFROST) {
- struct bifrost_texture_descriptor *descriptors;
+ struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool,
+ MALI_BIFROST_TEXTURE_LENGTH *
+ ctx->sampler_view_count[stage]);
- descriptors = malloc(sizeof(struct bifrost_texture_descriptor) *
- ctx->sampler_view_count[stage]);
+ struct mali_bifrost_texture_packed *out =
+ (struct mali_bifrost_texture_packed *) T.cpu;
for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) {
struct panfrost_sampler_view *view = ctx->sampler_views[stage][i];
struct pipe_sampler_view *pview = &view->base;
struct panfrost_resource *rsrc = pan_resource(pview->texture);
+
panfrost_update_sampler_view(view, &ctx->base);
+ out[i] = view->bifrost_descriptor;
/* Add the BOs to the job so they are retained until the job is done. */
panfrost_batch_add_bo(batch, view->bo,
PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
panfrost_bo_access_for_stage(stage));
-
- memcpy(&descriptors[i], view->bifrost_descriptor, sizeof(*view->bifrost_descriptor));
}
- postfix->textures = panfrost_pool_upload(&batch->pool,
- descriptors,
- sizeof(struct bifrost_texture_descriptor) *
- ctx->sampler_view_count[stage]);
-
- free(descriptors);
+ postfix->textures = T.gpu;
} else {
uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_context *ctx = batch->ctx;
- struct panfrost_device *device = pan_device(ctx->base.screen);
if (!ctx->sampler_count[stage])
return;
- if (device->quirks & IS_BIFROST) {
- size_t desc_size = sizeof(struct bifrost_sampler_descriptor);
- size_t transfer_size = desc_size * ctx->sampler_count[stage];
- struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool,
- transfer_size);
- struct bifrost_sampler_descriptor *desc = (struct bifrost_sampler_descriptor *)transfer.cpu;
+ size_t desc_size = MALI_BIFROST_SAMPLER_LENGTH;
+ assert(MALI_BIFROST_SAMPLER_LENGTH == MALI_MIDGARD_SAMPLER_LENGTH);
- for (int i = 0; i < ctx->sampler_count[stage]; ++i)
- desc[i] = ctx->samplers[stage][i]->bifrost_hw;
+ size_t sz = desc_size * ctx->sampler_count[stage];
+ struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, sz);
+ struct mali_midgard_sampler_packed *out = (struct mali_midgard_sampler_packed *) T.cpu;
- postfix->sampler_descriptor = transfer.gpu;
- } else {
- size_t desc_size = sizeof(struct mali_sampler_descriptor);
- size_t transfer_size = desc_size * ctx->sampler_count[stage];
- struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool,
- transfer_size);
- struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *)transfer.cpu;
+ for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i)
+ out[i] = ctx->samplers[stage][i]->hw;
- for (int i = 0; i < ctx->sampler_count[stage]; ++i)
- desc[i] = ctx->samplers[stage][i]->midgard_hw;
-
- postfix->sampler_descriptor = transfer.gpu;
- }
-}
-
-void
-panfrost_emit_vertex_attr_meta(struct panfrost_batch *batch,
- struct mali_vertex_tiler_postfix *vertex_postfix)
-{
- struct panfrost_context *ctx = batch->ctx;
-
- if (!ctx->vertex)
- return;
-
- struct panfrost_vertex_state *so = ctx->vertex;
-
- panfrost_vertex_state_upd_attr_offs(ctx, vertex_postfix);
- vertex_postfix->attribute_meta = panfrost_pool_upload(&batch->pool, so->hw,
- sizeof(*so->hw) *
- PAN_MAX_ATTRIBUTE);
+ postfix->sampler_descriptor = T.gpu;
}
void
* vertex buffer mask and instancing. Twice as much room is allocated,
* for a worst case of NPOT_DIVIDEs which take up extra slot */
union mali_attr attrs[PIPE_MAX_ATTRIBS * 2];
+ unsigned attrib_to_buffer[PIPE_MAX_ATTRIBS] = { 0 };
unsigned k = 0;
for (unsigned i = 0; i < so->num_elements; ++i) {
struct pipe_vertex_element *elem = &so->pipe[i];
unsigned vbi = elem->vertex_buffer_index;
-
- /* The exception to 1:1 mapping is that we can have multiple
- * entries (NPOT divisors), so we fixup anyways */
-
- so->hw[i].index = k;
+ attrib_to_buffer[i] = k;
if (!(ctx->vb_mask & (1 << vbi)))
continue;
/* Add special gl_VertexID/gl_InstanceID buffers */
+ struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool,
+ MALI_ATTRIBUTE_LENGTH * (PAN_INSTANCE_ID + 1));
+
+ struct mali_attribute_packed *out =
+ (struct mali_attribute_packed *) T.cpu;
+
panfrost_vertex_id(ctx->padded_count, &attrs[k]);
- so->hw[PAN_VERTEX_ID].index = k++;
+
+ pan_pack(out + PAN_VERTEX_ID, ATTRIBUTE, cfg) {
+ cfg.buffer_index = k++;
+ cfg.format = so->formats[PAN_VERTEX_ID];
+ }
+
panfrost_instance_id(ctx->padded_count, &attrs[k]);
- so->hw[PAN_INSTANCE_ID].index = k++;
- /* Upload whatever we emitted and go */
+ pan_pack(out + PAN_INSTANCE_ID, ATTRIBUTE, cfg) {
+ cfg.buffer_index = k++;
+ cfg.format = so->formats[PAN_INSTANCE_ID];
+ }
+
+ /* Attribute addresses require 64-byte alignment, so let:
+ *
+ * base' = base & ~63 = base - (base & 63)
+ * offset' = offset + (base & 63)
+ *
+ * Since base' + offset' = base + offset, these are equivalent
+ * addressing modes and now base is 64 aligned.
+ */
+
+ unsigned start = vertex_postfix->offset_start;
+
+ for (unsigned i = 0; i < so->num_elements; ++i) {
+ unsigned vbi = so->pipe[i].vertex_buffer_index;
+ struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
+
+ /* Adjust by the masked off bits of the offset. Make sure we
+ * read src_offset from so->hw (which is not GPU visible)
+ * rather than target (which is) due to caching effects */
+
+ unsigned src_offset = so->pipe[i].src_offset;
+
+ /* BOs aligned to 4k so guaranteed aligned to 64 */
+ src_offset += (buf->buffer_offset & 63);
+
+ /* Also, somewhat obscurely per-instance data needs to be
+ * offset in response to a delayed start in an indexed draw */
+
+ if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start)
+ src_offset -= buf->stride * start;
+
+ pan_pack(out + i, ATTRIBUTE, cfg) {
+ cfg.buffer_index = attrib_to_buffer[i];
+ cfg.format = so->formats[i];
+ cfg.offset = src_offset;
+ }
+ }
+
vertex_postfix->attributes = panfrost_pool_upload(&batch->pool, attrs,
k * sizeof(*attrs));
+
+ vertex_postfix->attribute_meta = T.gpu;
}
static mali_ptr
unsigned offset)
{
unsigned nr_channels = MALI_EXTRACT_CHANNELS(format);
+ unsigned swizzle = quirks & HAS_SWIZZLES ?
+ panfrost_get_default_swizzle(nr_channels) :
+ panfrost_bifrost_swizzle(nr_channels);
struct mali_attr_meta meta = {
.index = pan_varying_index(present, buf),
.unknown1 = quirks & IS_BIFROST ? 0x0 : 0x2,
- .swizzle = quirks & HAS_SWIZZLES ?
- panfrost_get_default_swizzle(nr_channels) :
- panfrost_bifrost_swizzle(nr_channels),
- .format = format,
+ .format = (format << 12) | swizzle,
.src_offset = offset
};
enum mali_format format,
struct pipe_stream_output o)
{
+ unsigned swizzle = quirks & HAS_SWIZZLES ?
+ panfrost_get_default_swizzle(o.num_components) :
+ panfrost_bifrost_swizzle(o.num_components);
+
/* Otherwise construct a record for it */
struct mali_attr_meta meta = {
/* XFB buffers come after everything else */
/* As usual unknown bit */
.unknown1 = quirks & IS_BIFROST ? 0x0 : 0x2,
- /* Override swizzle with number of channels */
- .swizzle = quirks & HAS_SWIZZLES ?
- panfrost_get_default_swizzle(o.num_components) :
- panfrost_bifrost_swizzle(o.num_components),
-
/* Override number of channels and precision to highp */
- .format = pan_xfb_format(format, o.num_components),
+ .format = (pan_xfb_format(format, o.num_components) << 12) | swizzle,
/* Apply given offsets together */
.src_offset = (o.dst_offset * 4) /* dwords */
projects / mesa.git / blobdiff