#include "panfrost-quirks.h"
-#include "pan_allocate.h"
+#include "pan_pool.h"
#include "pan_bo.h"
#include "pan_cmdstream.h"
#include "pan_context.h"
.scratchpad = panfrost_batch_get_scratchpad(batch, shift, dev->thread_tls_alloc, dev->core_count)->gpu,
.shared_workgroup_count = ~0,
};
- postfix->shared_memory = panfrost_upload_transient(batch, &shared, sizeof(shared));
+ postfix->shared_memory = panfrost_pool_upload(&batch->pool, &shared, sizeof(shared));
}
static void
panfrost_vt_attach_framebuffer(struct panfrost_context *ctx,
struct mali_vertex_tiler_postfix *postfix)
{
- struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
-
- /* If we haven't, reserve space for the framebuffer */
-
- if (!batch->framebuffer.gpu) {
- unsigned size = (dev->quirks & MIDGARD_SFBD) ?
- sizeof(struct mali_single_framebuffer) :
- sizeof(struct mali_framebuffer);
-
- batch->framebuffer = panfrost_allocate_transient(batch, size);
-
- /* Tag the pointer */
- if (!(dev->quirks & MIDGARD_SFBD))
- batch->framebuffer.gpu |= MALI_MFBD;
- }
-
- postfix->shared_memory = batch->framebuffer.gpu;
+ postfix->shared_memory = panfrost_batch_reserve_framebuffer(batch);
}
static void
struct panfrost_rasterizer *rasterizer = ctx->rasterizer;
if (!panfrost_writes_point_size(ctx)) {
- bool points = prefix->draw_mode == MALI_POINTS;
+ bool points = prefix->draw_mode == MALI_DRAW_MODE_POINTS;
float val = 0.0f;
if (rasterizer)
} else {
/* Otherwise, we need to upload to transient memory */
const uint8_t *ibuf8 = (const uint8_t *) info->index.user;
- out = panfrost_upload_transient(batch, ibuf8 + offset,
+ out = panfrost_pool_upload(&batch->pool, ibuf8 + offset,
info->count *
info->index_size);
}
}
static unsigned
-panfrost_translate_compare_func(enum pipe_compare_func in)
+translate_tex_wrap(enum pipe_tex_wrap w)
{
- switch (in) {
- case PIPE_FUNC_NEVER:
- return MALI_FUNC_NEVER;
-
- case PIPE_FUNC_LESS:
- return MALI_FUNC_LESS;
-
- case PIPE_FUNC_EQUAL:
- return MALI_FUNC_EQUAL;
-
- case PIPE_FUNC_LEQUAL:
- return MALI_FUNC_LEQUAL;
-
- case PIPE_FUNC_GREATER:
- return MALI_FUNC_GREATER;
-
- case PIPE_FUNC_NOTEQUAL:
- return MALI_FUNC_NOTEQUAL;
-
- case PIPE_FUNC_GEQUAL:
- return MALI_FUNC_GEQUAL;
-
- case PIPE_FUNC_ALWAYS:
- return MALI_FUNC_ALWAYS;
-
- default:
- unreachable("Invalid func");
+ switch (w) {
+ case PIPE_TEX_WRAP_REPEAT: return MALI_WRAP_MODE_REPEAT;
+ case PIPE_TEX_WRAP_CLAMP: return MALI_WRAP_MODE_CLAMP;
+ case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return MALI_WRAP_MODE_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return MALI_WRAP_MODE_CLAMP_TO_BORDER;
+ case PIPE_TEX_WRAP_MIRROR_REPEAT: return MALI_WRAP_MODE_MIRRORED_REPEAT;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP: return MALI_WRAP_MODE_MIRRORED_CLAMP;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER;
+ default: unreachable("Invalid wrap");
}
}
-static unsigned
-panfrost_translate_stencil_op(enum pipe_stencil_op in)
-{
- switch (in) {
- case PIPE_STENCIL_OP_KEEP:
- return MALI_STENCIL_KEEP;
-
- case PIPE_STENCIL_OP_ZERO:
- return MALI_STENCIL_ZERO;
-
- case PIPE_STENCIL_OP_REPLACE:
- return MALI_STENCIL_REPLACE;
-
- case PIPE_STENCIL_OP_INCR:
- return MALI_STENCIL_INCR;
-
- case PIPE_STENCIL_OP_DECR:
- return MALI_STENCIL_DECR;
+/* The hardware compares in the wrong order order, so we have to flip before
+ * encoding. Yes, really. */
- case PIPE_STENCIL_OP_INCR_WRAP:
- return MALI_STENCIL_INCR_WRAP;
-
- case PIPE_STENCIL_OP_DECR_WRAP:
- return MALI_STENCIL_DECR_WRAP;
+static enum mali_func
+panfrost_sampler_compare_func(const struct pipe_sampler_state *cso)
+{
+ if (!cso->compare_mode)
+ return MALI_FUNC_NEVER;
- case PIPE_STENCIL_OP_INVERT:
- return MALI_STENCIL_INVERT;
+ enum mali_func f = panfrost_translate_compare_func(cso->compare_func);
+ return panfrost_flip_compare_func(f);
+}
- default:
- unreachable("Invalid stencil op");
+static enum mali_mipmap_mode
+pan_pipe_to_mipmode(enum pipe_tex_mipfilter f)
+{
+ switch (f) {
+ case PIPE_TEX_MIPFILTER_NEAREST: return MALI_MIPMAP_MODE_NEAREST;
+ case PIPE_TEX_MIPFILTER_LINEAR: return MALI_MIPMAP_MODE_TRILINEAR;
+ case PIPE_TEX_MIPFILTER_NONE: return MALI_MIPMAP_MODE_NONE;
+ default: unreachable("Invalid");
}
}
-static unsigned
-translate_tex_wrap(enum pipe_tex_wrap w)
+void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso,
+ struct mali_midgard_sampler_packed *hw)
{
- switch (w) {
- case PIPE_TEX_WRAP_REPEAT:
- return MALI_WRAP_REPEAT;
+ pan_pack(hw, MIDGARD_SAMPLER, cfg) {
+ cfg.magnify_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
+ cfg.minify_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
+ cfg.mipmap_mode = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR) ?
+ MALI_MIPMAP_MODE_TRILINEAR : MALI_MIPMAP_MODE_NEAREST;
+ cfg.normalized_coordinates = cso->normalized_coords;
- case PIPE_TEX_WRAP_CLAMP:
- return MALI_WRAP_CLAMP;
+ cfg.lod_bias = FIXED_16(cso->lod_bias, true);
- case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
- return MALI_WRAP_CLAMP_TO_EDGE;
+ cfg.minimum_lod = FIXED_16(cso->min_lod, false);
- case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
- return MALI_WRAP_CLAMP_TO_BORDER;
+ /* If necessary, we disable mipmapping in the sampler descriptor by
+ * clamping the LOD as tight as possible (from 0 to epsilon,
+ * essentially -- remember these are fixed point numbers, so
+ * epsilon=1/256) */
- case PIPE_TEX_WRAP_MIRROR_REPEAT:
- return MALI_WRAP_MIRRORED_REPEAT;
+ cfg.maximum_lod = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) ?
+ cfg.minimum_lod + 1 :
+ FIXED_16(cso->max_lod, false);
- case PIPE_TEX_WRAP_MIRROR_CLAMP:
- return MALI_WRAP_MIRRORED_CLAMP;
+ cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s);
+ cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t);
+ cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r);
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
- return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE;
+ cfg.compare_function = panfrost_sampler_compare_func(cso);
+ cfg.seamless_cube_map = cso->seamless_cube_map;
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
- return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER;
-
- default:
- unreachable("Invalid wrap");
+ cfg.border_color_r = cso->border_color.f[0];
+ cfg.border_color_g = cso->border_color.f[1];
+ cfg.border_color_b = cso->border_color.f[2];
+ cfg.border_color_a = cso->border_color.f[3];
}
}
-void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso,
- struct mali_sampler_descriptor *hw)
-{
- unsigned func = panfrost_translate_compare_func(cso->compare_func);
- bool min_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
- bool mag_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
- bool mip_linear = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR;
- unsigned min_filter = min_nearest ? MALI_SAMP_MIN_NEAREST : 0;
- unsigned mag_filter = mag_nearest ? MALI_SAMP_MAG_NEAREST : 0;
- unsigned mip_filter = mip_linear ?
- (MALI_SAMP_MIP_LINEAR_1 | MALI_SAMP_MIP_LINEAR_2) : 0;
- unsigned normalized = cso->normalized_coords ? MALI_SAMP_NORM_COORDS : 0;
-
- *hw = (struct mali_sampler_descriptor) {
- .filter_mode = min_filter | mag_filter | mip_filter |
- normalized,
- .wrap_s = translate_tex_wrap(cso->wrap_s),
- .wrap_t = translate_tex_wrap(cso->wrap_t),
- .wrap_r = translate_tex_wrap(cso->wrap_r),
- .compare_func = panfrost_flip_compare_func(func),
- .border_color = {
- cso->border_color.f[0],
- cso->border_color.f[1],
- cso->border_color.f[2],
- cso->border_color.f[3]
- },
- .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */
- .max_lod = FIXED_16(cso->max_lod, false),
- .lod_bias = FIXED_16(cso->lod_bias, true), /* can be negative */
- .seamless_cube_map = cso->seamless_cube_map,
- };
-
- /* If necessary, we disable mipmapping in the sampler descriptor by
- * clamping the LOD as tight as possible (from 0 to epsilon,
- * essentially -- remember these are fixed point numbers, so
- * epsilon=1/256) */
-
- if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
- hw->max_lod = hw->min_lod + 1;
-}
-
void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso,
- struct bifrost_sampler_descriptor *hw)
-{
- *hw = (struct bifrost_sampler_descriptor) {
- .unk1 = 0x1,
- .wrap_s = translate_tex_wrap(cso->wrap_s),
- .wrap_t = translate_tex_wrap(cso->wrap_t),
- .wrap_r = translate_tex_wrap(cso->wrap_r),
- .unk8 = 0x8,
- .min_filter = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST,
- .norm_coords = cso->normalized_coords,
- .mip_filter = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR,
- .mag_filter = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR,
- .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */
- .max_lod = FIXED_16(cso->max_lod, false),
- };
-
- /* If necessary, we disable mipmapping in the sampler descriptor by
- * clamping the LOD as tight as possible (from 0 to epsilon,
- * essentially -- remember these are fixed point numbers, so
- * epsilon=1/256) */
-
- if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
- hw->max_lod = hw->min_lod + 1;
-}
-
-static void
-panfrost_make_stencil_state(const struct pipe_stencil_state *in,
- struct mali_stencil_test *out)
+ struct mali_bifrost_sampler_packed *hw)
{
- out->ref = 0; /* Gallium gets it from elsewhere */
-
- out->mask = in->valuemask;
- out->func = panfrost_translate_compare_func(in->func);
- out->sfail = panfrost_translate_stencil_op(in->fail_op);
- out->dpfail = panfrost_translate_stencil_op(in->zfail_op);
- out->dppass = panfrost_translate_stencil_op(in->zpass_op);
+ pan_pack(hw, BIFROST_SAMPLER, cfg) {
+ cfg.magnify_linear = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR;
+ cfg.minify_linear = cso->min_img_filter == PIPE_TEX_FILTER_LINEAR;
+ cfg.mipmap_mode = pan_pipe_to_mipmode(cso->min_mip_filter);
+ cfg.normalized_coordinates = cso->normalized_coords;
+
+ cfg.lod_bias = FIXED_16(cso->lod_bias, true);
+ cfg.minimum_lod = FIXED_16(cso->min_lod, false);
+ cfg.maximum_lod = FIXED_16(cso->max_lod, false);
+
+ cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s);
+ cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t);
+ cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r);
+
+ cfg.compare_function = panfrost_sampler_compare_func(cso);
+ cfg.seamless_cube_map = cso->seamless_cube_map;
+ }
}
static void
/* TODO: Sample size */
SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa);
SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa);
+
+ struct panfrost_shader_state *fs;
+ fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
+
+ /* EXT_shader_framebuffer_fetch requires the shader to be run
+ * per-sample when outputs are read. */
+ bool per_sample = ctx->min_samples > 1 || fs->outputs_read;
+ SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample);
+
fragmeta->depth_units = rast->offset_units * 2.0f;
fragmeta->depth_factor = rast->offset_scale;
panfrost_frag_meta_zsa_update(struct panfrost_context *ctx,
struct mali_shader_meta *fragmeta)
{
- const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil;
+ const struct panfrost_zsa_state *so = ctx->depth_stencil;
int zfunc = PIPE_FUNC_ALWAYS;
- if (!zsa) {
- struct pipe_stencil_state default_stencil = {
- .enabled = 0,
- .func = PIPE_FUNC_ALWAYS,
- .fail_op = MALI_STENCIL_KEEP,
- .zfail_op = MALI_STENCIL_KEEP,
- .zpass_op = MALI_STENCIL_KEEP,
- .writemask = 0xFF,
- .valuemask = 0xFF
- };
-
- panfrost_make_stencil_state(&default_stencil,
- &fragmeta->stencil_front);
- fragmeta->stencil_mask_front = default_stencil.writemask;
- fragmeta->stencil_back = fragmeta->stencil_front;
- fragmeta->stencil_mask_back = default_stencil.writemask;
+ if (!so) {
+ /* If stenciling is disabled, the state is irrelevant */
SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, false);
SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, false);
} else {
SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST,
- zsa->stencil[0].enabled);
- panfrost_make_stencil_state(&zsa->stencil[0],
- &fragmeta->stencil_front);
- fragmeta->stencil_mask_front = zsa->stencil[0].writemask;
- fragmeta->stencil_front.ref = ctx->stencil_ref.ref_value[0];
+ so->base.stencil[0].enabled);
+
+ fragmeta->stencil_mask_front = so->stencil_mask_front;
+ fragmeta->stencil_mask_back = so->stencil_mask_back;
+
+ /* Bottom bits for stencil ref, exactly one word */
+ fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0];
/* If back-stencil is not enabled, use the front values */
- if (zsa->stencil[1].enabled) {
- panfrost_make_stencil_state(&zsa->stencil[1],
- &fragmeta->stencil_back);
- fragmeta->stencil_mask_back = zsa->stencil[1].writemask;
- fragmeta->stencil_back.ref = ctx->stencil_ref.ref_value[1];
- } else {
+ if (so->base.stencil[1].enabled)
+ fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1];
+ else
fragmeta->stencil_back = fragmeta->stencil_front;
- fragmeta->stencil_mask_back = fragmeta->stencil_mask_front;
- fragmeta->stencil_back.ref = fragmeta->stencil_front.ref;
- }
- if (zsa->depth.enabled)
- zfunc = zsa->depth.func;
+ if (so->base.depth.enabled)
+ zfunc = so->base.depth.func;
/* Depth state (TODO: Refactor) */
SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK,
- zsa->depth.writemask);
+ so->base.depth.writemask);
}
fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
struct mali_shader_meta *fragmeta,
void *rts)
{
+ struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
const struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_shader_state *fs;
fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD,
!blend[0].no_blending || fs->can_discard);
+
+ batch->draws |= PIPE_CLEAR_COLOR0;
return;
}
if (ctx->pipe_framebuffer.nr_cbufs > i && !blend[i].no_colour) {
flags = 0x200;
+ batch->draws |= (PIPE_CLEAR_COLOR0 << i);
bool is_srgb = (ctx->pipe_framebuffer.nr_cbufs > i) &&
(ctx->pipe_framebuffer.cbufs[i]) &&
fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
bool msaa = ctx->rasterizer && ctx->rasterizer->base.multisample;
- fragmeta->coverage_mask = (msaa ? ctx->sample_mask : ~0) & 0xF;
+ fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0;
fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10;
fragmeta->unknown2_4 = 0x4e0;
SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS,
fs->helper_invocations);
- const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil;
+ /* If discard is enabled, which bit we set to convey this
+ * depends on if depth/stencil is used for the draw or not.
+ * Just one of depth OR stencil is enough to trigger this. */
- bool depth_enabled = fs->writes_depth ||
- (zsa && zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS);
+ const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base;
+ bool zs_enabled = fs->writes_depth || fs->writes_stencil;
- SET_BIT(fragmeta->midgard1.flags_lo, 0x400, !depth_enabled && fs->can_discard);
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, depth_enabled && fs->can_discard);
+ if (zsa) {
+ zs_enabled |= (zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS);
+ zs_enabled |= zsa->stencil[0].enabled;
+ }
+
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER,
+ fs->outputs_read || (!zs_enabled && fs->can_discard));
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard);
}
panfrost_frag_meta_rasterizer_update(ctx, fragmeta);
panfrost_frag_shader_meta_init(ctx, &meta, rts);
- xfer = panfrost_allocate_transient(batch, desc_size);
+ xfer = panfrost_pool_alloc(&batch->pool, desc_size);
memcpy(xfer.cpu, &meta, sizeof(meta));
memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count);
shader_ptr = xfer.gpu;
} else {
- shader_ptr = panfrost_upload_transient(batch, &meta,
+ shader_ptr = panfrost_pool_upload(&batch->pool, &meta,
sizeof(meta));
}
postfix->shader = shader_ptr;
}
-static void
-panfrost_mali_viewport_init(struct panfrost_context *ctx,
- struct mali_viewport *mvp)
+void
+panfrost_emit_viewport(struct panfrost_batch *batch,
+ struct mali_vertex_tiler_postfix *tiler_postfix)
{
+ struct panfrost_context *ctx = batch->ctx;
const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
-
- /* Clip bounds are encoded as floats. The viewport itself is encoded as
- * (somewhat) asymmetric ints. */
-
const struct pipe_scissor_state *ss = &ctx->scissor;
+ const struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
+ const struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
- memset(mvp, 0, sizeof(*mvp));
-
- /* By default, do no viewport clipping, i.e. clip to (-inf, inf) in
- * each direction. Clipping to the viewport in theory should work, but
- * in practice causes issues when we're not explicitly trying to
- * scissor */
-
- *mvp = (struct mali_viewport) {
- .clip_minx = -INFINITY,
- .clip_miny = -INFINITY,
- .clip_maxx = INFINITY,
- .clip_maxy = INFINITY,
- };
-
- /* Always scissor to the viewport by default. */
+ /* Derive min/max from translate/scale. Note since |x| >= 0 by
+ * definition, we have that -|x| <= |x| hence translate - |scale| <=
+ * translate + |scale|, so the ordering is correct here. */
float vp_minx = (int) (vp->translate[0] - fabsf(vp->scale[0]));
float vp_maxx = (int) (vp->translate[0] + fabsf(vp->scale[0]));
-
float vp_miny = (int) (vp->translate[1] - fabsf(vp->scale[1]));
float vp_maxy = (int) (vp->translate[1] + fabsf(vp->scale[1]));
-
float minz = (vp->translate[2] - fabsf(vp->scale[2]));
float maxz = (vp->translate[2] + fabsf(vp->scale[2]));
- /* Apply the scissor test */
-
- unsigned minx, miny, maxx, maxy;
-
- if (ss && ctx->rasterizer && ctx->rasterizer->base.scissor) {
- minx = MAX2(ss->minx, vp_minx);
- miny = MAX2(ss->miny, vp_miny);
- maxx = MIN2(ss->maxx, vp_maxx);
- maxy = MIN2(ss->maxy, vp_maxy);
- } else {
- minx = vp_minx;
- miny = vp_miny;
- maxx = vp_maxx;
- maxy = vp_maxy;
- }
-
- /* Hardware needs the min/max to be strictly ordered, so flip if we
- * need to. The viewport transformation in the vertex shader will
- * handle the negatives if we don't */
+ /* Scissor to the intersection of viewport and to the scissor, clamped
+ * to the framebuffer */
- if (miny > maxy) {
- unsigned temp = miny;
- miny = maxy;
- maxy = temp;
- }
-
- if (minx > maxx) {
- unsigned temp = minx;
- minx = maxx;
- maxx = temp;
- }
+ unsigned minx = MIN2(fb->width, vp_minx);
+ unsigned maxx = MIN2(fb->width, vp_maxx);
+ unsigned miny = MIN2(fb->height, vp_miny);
+ unsigned maxy = MIN2(fb->height, vp_maxy);
- if (minz > maxz) {
- float temp = minz;
- minz = maxz;
- maxz = temp;
+ if (ss && rast && rast->scissor) {
+ minx = MAX2(ss->minx, minx);
+ miny = MAX2(ss->miny, miny);
+ maxx = MIN2(ss->maxx, maxx);
+ maxy = MIN2(ss->maxy, maxy);
}
- /* Clamp to the framebuffer size as a last check */
+ struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, MALI_VIEWPORT_LENGTH);
- minx = MIN2(ctx->pipe_framebuffer.width, minx);
- maxx = MIN2(ctx->pipe_framebuffer.width, maxx);
+ pan_pack(T.cpu, VIEWPORT, cfg) {
+ cfg.scissor_minimum_x = minx;
+ cfg.scissor_minimum_y = miny;
+ cfg.scissor_maximum_x = maxx - 1;
+ cfg.scissor_maximum_y = maxy - 1;
- miny = MIN2(ctx->pipe_framebuffer.height, miny);
- maxy = MIN2(ctx->pipe_framebuffer.height, maxy);
-
- /* Upload */
-
- mvp->viewport0[0] = minx;
- mvp->viewport1[0] = MALI_POSITIVE(maxx);
-
- mvp->viewport0[1] = miny;
- mvp->viewport1[1] = MALI_POSITIVE(maxy);
-
- bool clip_near = true;
- bool clip_far = true;
-
- if (ctx->rasterizer) {
- clip_near = ctx->rasterizer->base.depth_clip_near;
- clip_far = ctx->rasterizer->base.depth_clip_far;
+ cfg.minimum_z = rast->depth_clip_near ? minz : -INFINITY;
+ cfg.maximum_z = rast->depth_clip_far ? maxz : INFINITY;
}
- mvp->clip_minz = clip_near ? minz : -INFINITY;
- mvp->clip_maxz = clip_far ? maxz : INFINITY;
-}
-
-void
-panfrost_emit_viewport(struct panfrost_batch *batch,
- struct mali_vertex_tiler_postfix *tiler_postfix)
-{
- struct panfrost_context *ctx = batch->ctx;
- struct mali_viewport mvp;
-
- panfrost_mali_viewport_init(batch->ctx, &mvp);
-
- /* Update the job, unless we're doing wallpapering (whose lack of
- * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
- * just... be faster :) */
-
- if (!ctx->wallpaper_batch)
- panfrost_batch_union_scissor(batch, mvp.viewport0[0],
- mvp.viewport0[1],
- mvp.viewport1[0] + 1,
- mvp.viewport1[1] + 1);
-
- tiler_postfix->viewport = panfrost_upload_transient(batch, &mvp,
- sizeof(mvp));
+ tiler_postfix->viewport = T.gpu;
+ panfrost_batch_union_scissor(batch, minx, miny, maxx, maxy);
}
static mali_ptr
* PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
return rsrc->bo->gpu + cb->buffer_offset;
} else if (cb->user_buffer) {
- return panfrost_upload_transient(batch,
+ return panfrost_pool_upload(&batch->pool,
cb->user_buffer +
cb->buffer_offset,
cb->buffer_size);
size_t sys_size = sizeof(float) * 4 * ss->sysval_count;
size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0;
size_t size = sys_size + uniform_size;
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
+ struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool,
size);
/* Upload sysvals requested by the shader */
unsigned ubo_count = panfrost_ubo_count(ctx, stage);
assert(ubo_count >= 1);
- size_t sz = sizeof(uint64_t) * ubo_count;
- uint64_t ubos[PAN_MAX_CONST_BUFFERS];
- int uniform_count = ss->uniform_count;
+ size_t sz = MALI_UNIFORM_BUFFER_LENGTH * ubo_count;
+ struct panfrost_transfer ubos = panfrost_pool_alloc(&batch->pool, sz);
+ uint64_t *ubo_ptr = (uint64_t *) ubos.cpu;
/* Upload uniforms as a UBO */
- ubos[0] = MALI_MAKE_UBO(2 + uniform_count, transfer.gpu);
+
+ if (ss->uniform_count) {
+ pan_pack(ubo_ptr, UNIFORM_BUFFER, cfg) {
+ cfg.entries = ss->uniform_count;
+ cfg.pointer = transfer.gpu;
+ }
+ } else {
+ *ubo_ptr = 0;
+ }
/* The rest are honest-to-goodness UBOs */
bool empty = usz == 0;
if (!enabled || empty) {
- /* Stub out disabled UBOs to catch accesses */
- ubos[ubo] = MALI_MAKE_UBO(0, 0xDEAD0000);
+ ubo_ptr[ubo] = 0;
continue;
}
- mali_ptr gpu = panfrost_map_constant_buffer_gpu(batch, stage,
- buf, ubo);
-
- unsigned bytes_per_field = 16;
- unsigned aligned = ALIGN_POT(usz, bytes_per_field);
- ubos[ubo] = MALI_MAKE_UBO(aligned / bytes_per_field, gpu);
+ pan_pack(ubo_ptr + ubo, UNIFORM_BUFFER, cfg) {
+ cfg.entries = DIV_ROUND_UP(usz, 16);
+ cfg.pointer = panfrost_map_constant_buffer_gpu(batch,
+ stage, buf, ubo);
+ }
}
- mali_ptr ubufs = panfrost_upload_transient(batch, ubos, sz);
postfix->uniforms = transfer.gpu;
- postfix->uniform_buffers = ubufs;
+ postfix->uniform_buffers = ubos.gpu;
buf->dirty_mask = 0;
}
.shared_shift = util_logbase2(single_size) - 1
};
- vtp->postfix.shared_memory = panfrost_upload_transient(batch, &shared,
+ vtp->postfix.shared_memory = panfrost_pool_upload(&batch->pool, &shared,
sizeof(shared));
}
{
struct panfrost_resource *rsrc = pan_resource(view->base.texture);
if (view->texture_bo != rsrc->bo->gpu ||
- view->layout != rsrc->layout) {
+ view->modifier != rsrc->modifier) {
panfrost_bo_unreference(view->bo);
panfrost_create_sampler_view_bo(view, pctx, &rsrc->base);
}
return;
if (device->quirks & IS_BIFROST) {
- struct bifrost_texture_descriptor *descriptors;
+ struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool,
+ MALI_BIFROST_TEXTURE_LENGTH *
+ ctx->sampler_view_count[stage]);
- descriptors = malloc(sizeof(struct bifrost_texture_descriptor) *
- ctx->sampler_view_count[stage]);
+ struct mali_bifrost_texture_packed *out =
+ (struct mali_bifrost_texture_packed *) T.cpu;
for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) {
struct panfrost_sampler_view *view = ctx->sampler_views[stage][i];
struct pipe_sampler_view *pview = &view->base;
struct panfrost_resource *rsrc = pan_resource(pview->texture);
+
panfrost_update_sampler_view(view, &ctx->base);
+ out[i] = view->bifrost_descriptor;
/* Add the BOs to the job so they are retained until the job is done. */
panfrost_batch_add_bo(batch, view->bo,
PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
panfrost_bo_access_for_stage(stage));
-
- memcpy(&descriptors[i], view->bifrost_descriptor, sizeof(*view->bifrost_descriptor));
}
- postfix->textures = panfrost_upload_transient(batch,
- descriptors,
- sizeof(struct bifrost_texture_descriptor) *
- ctx->sampler_view_count[stage]);
-
- free(descriptors);
+ postfix->textures = T.gpu;
} else {
uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
trampolines[i] = panfrost_get_tex_desc(batch, stage, view);
}
- postfix->textures = panfrost_upload_transient(batch,
+ postfix->textures = panfrost_pool_upload(&batch->pool,
trampolines,
sizeof(uint64_t) *
ctx->sampler_view_count[stage]);
struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_context *ctx = batch->ctx;
- struct panfrost_device *device = pan_device(ctx->base.screen);
if (!ctx->sampler_count[stage])
return;
- if (device->quirks & IS_BIFROST) {
- size_t desc_size = sizeof(struct bifrost_sampler_descriptor);
- size_t transfer_size = desc_size * ctx->sampler_count[stage];
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
- transfer_size);
- struct bifrost_sampler_descriptor *desc = (struct bifrost_sampler_descriptor *)transfer.cpu;
-
- for (int i = 0; i < ctx->sampler_count[stage]; ++i)
- desc[i] = ctx->samplers[stage][i]->bifrost_hw;
-
- postfix->sampler_descriptor = transfer.gpu;
- } else {
- size_t desc_size = sizeof(struct mali_sampler_descriptor);
- size_t transfer_size = desc_size * ctx->sampler_count[stage];
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
- transfer_size);
- struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *)transfer.cpu;
-
- for (int i = 0; i < ctx->sampler_count[stage]; ++i)
- desc[i] = ctx->samplers[stage][i]->midgard_hw;
-
- postfix->sampler_descriptor = transfer.gpu;
- }
-}
-
-void
-panfrost_emit_vertex_attr_meta(struct panfrost_batch *batch,
- struct mali_vertex_tiler_postfix *vertex_postfix)
-{
- struct panfrost_context *ctx = batch->ctx;
+ size_t desc_size = MALI_BIFROST_SAMPLER_LENGTH;
+ assert(MALI_BIFROST_SAMPLER_LENGTH == MALI_MIDGARD_SAMPLER_LENGTH);
- if (!ctx->vertex)
- return;
+ size_t sz = desc_size * ctx->sampler_count[stage];
+ struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, sz);
+ struct mali_midgard_sampler_packed *out = (struct mali_midgard_sampler_packed *) T.cpu;
- struct panfrost_vertex_state *so = ctx->vertex;
+ for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i)
+ out[i] = ctx->samplers[stage][i]->hw;
- panfrost_vertex_state_upd_attr_offs(ctx, vertex_postfix);
- vertex_postfix->attribute_meta = panfrost_upload_transient(batch, so->hw,
- sizeof(*so->hw) *
- PAN_MAX_ATTRIBUTE);
+ postfix->sampler_descriptor = T.gpu;
}
void
* vertex buffer mask and instancing. Twice as much room is allocated,
* for a worst case of NPOT_DIVIDEs which take up extra slot */
union mali_attr attrs[PIPE_MAX_ATTRIBS * 2];
+ unsigned attrib_to_buffer[PIPE_MAX_ATTRIBS] = { 0 };
unsigned k = 0;
for (unsigned i = 0; i < so->num_elements; ++i) {
struct pipe_vertex_element *elem = &so->pipe[i];
unsigned vbi = elem->vertex_buffer_index;
-
- /* The exception to 1:1 mapping is that we can have multiple
- * entries (NPOT divisors), so we fixup anyways */
-
- so->hw[i].index = k;
+ attrib_to_buffer[i] = k;
if (!(ctx->vb_mask & (1 << vbi)))
continue;
/* Add special gl_VertexID/gl_InstanceID buffers */
+ struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool,
+ MALI_ATTRIBUTE_LENGTH * (PAN_INSTANCE_ID + 1));
+
+ struct mali_attribute_packed *out =
+ (struct mali_attribute_packed *) T.cpu;
+
panfrost_vertex_id(ctx->padded_count, &attrs[k]);
- so->hw[PAN_VERTEX_ID].index = k++;
+
+ pan_pack(out + PAN_VERTEX_ID, ATTRIBUTE, cfg) {
+ cfg.buffer_index = k++;
+ cfg.format = so->formats[PAN_VERTEX_ID];
+ }
+
panfrost_instance_id(ctx->padded_count, &attrs[k]);
- so->hw[PAN_INSTANCE_ID].index = k++;
- /* Upload whatever we emitted and go */
+ pan_pack(out + PAN_INSTANCE_ID, ATTRIBUTE, cfg) {
+ cfg.buffer_index = k++;
+ cfg.format = so->formats[PAN_INSTANCE_ID];
+ }
+
+ /* Attribute addresses require 64-byte alignment, so let:
+ *
+ * base' = base & ~63 = base - (base & 63)
+ * offset' = offset + (base & 63)
+ *
+ * Since base' + offset' = base + offset, these are equivalent
+ * addressing modes and now base is 64 aligned.
+ */
+
+ unsigned start = vertex_postfix->offset_start;
+
+ for (unsigned i = 0; i < so->num_elements; ++i) {
+ unsigned vbi = so->pipe[i].vertex_buffer_index;
+ struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
+
+ /* Adjust by the masked off bits of the offset. Make sure we
+ * read src_offset from so->hw (which is not GPU visible)
+ * rather than target (which is) due to caching effects */
+
+ unsigned src_offset = so->pipe[i].src_offset;
+
+ /* BOs aligned to 4k so guaranteed aligned to 64 */
+ src_offset += (buf->buffer_offset & 63);
+
+ /* Also, somewhat obscurely per-instance data needs to be
+ * offset in response to a delayed start in an indexed draw */
+
+ if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start)
+ src_offset -= buf->stride * start;
+
+ pan_pack(out + i, ATTRIBUTE, cfg) {
+ cfg.buffer_index = attrib_to_buffer[i];
+ cfg.format = so->formats[i];
+ cfg.offset = src_offset;
+ }
+ }
+
- vertex_postfix->attributes = panfrost_upload_transient(batch, attrs,
+ vertex_postfix->attributes = panfrost_pool_upload(&batch->pool, attrs,
k * sizeof(*attrs));
+
+ vertex_postfix->attribute_meta = T.gpu;
}
static mali_ptr
slot->size = stride * count;
slot->shift = slot->extra_flags = 0;
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
+ struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool,
slot->size);
slot->elements = transfer.gpu | MALI_ATTR_LINEAR;
unsigned offset)
{
unsigned nr_channels = MALI_EXTRACT_CHANNELS(format);
+ unsigned swizzle = quirks & HAS_SWIZZLES ?
+ panfrost_get_default_swizzle(nr_channels) :
+ panfrost_bifrost_swizzle(nr_channels);
struct mali_attr_meta meta = {
.index = pan_varying_index(present, buf),
.unknown1 = quirks & IS_BIFROST ? 0x0 : 0x2,
- .swizzle = quirks & HAS_SWIZZLES ?
- panfrost_get_default_swizzle(nr_channels) :
- panfrost_bifrost_swizzle(nr_channels),
- .format = format,
+ .format = (format << 12) | swizzle,
.src_offset = offset
};
enum mali_format format,
struct pipe_stream_output o)
{
+ unsigned swizzle = quirks & HAS_SWIZZLES ?
+ panfrost_get_default_swizzle(o.num_components) :
+ panfrost_bifrost_swizzle(o.num_components);
+
/* Otherwise construct a record for it */
struct mali_attr_meta meta = {
/* XFB buffers come after everything else */
/* As usual unknown bit */
.unknown1 = quirks & IS_BIFROST ? 0x0 : 0x2,
- /* Override swizzle with number of channels */
- .swizzle = quirks & HAS_SWIZZLES ?
- panfrost_get_default_swizzle(o.num_components) :
- panfrost_bifrost_swizzle(o.num_components),
-
/* Override number of channels and precision to highp */
- .format = pan_xfb_format(format, o.num_components),
+ .format = (pan_xfb_format(format, o.num_components) << 12) | swizzle,
/* Apply given offsets together */
.src_offset = (o.dst_offset * 4) /* dwords */
vs_size = sizeof(struct mali_attr_meta) * vs->varying_count;
fs_size = sizeof(struct mali_attr_meta) * fs->varying_count;
- struct panfrost_transfer trans = panfrost_allocate_transient(batch,
+ struct panfrost_transfer trans = panfrost_pool_alloc(&batch->pool,
vs_size +
fs_size);
}
unsigned xfb_base = pan_xfb_base(present);
- struct panfrost_transfer T = panfrost_allocate_transient(batch,
+ struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool,
sizeof(union mali_attr) * (xfb_base + ctx->streamout.num_targets));
union mali_attr *varyings = (union mali_attr *) T.cpu;
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_device *device = pan_device(ctx->base.screen);
- bool wallpapering = ctx->wallpaper_batch && batch->tiler_dep;
+ bool wallpapering = ctx->wallpaper_batch && batch->scoreboard.tiler_dep;
struct bifrost_payload_vertex bifrost_vertex = {0,};
struct bifrost_payload_tiler bifrost_tiler = {0,};
struct midgard_payload_vertex_tiler midgard_vertex = {0,};
if (wallpapering) {
/* Inject in reverse order, with "predicted" job indices.
* THIS IS A HACK XXX */
- panfrost_new_job(batch, JOB_TYPE_TILER, false,
- batch->job_index + 2, tp, tp_size, true);
- panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0,
+ panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false,
+ batch->scoreboard.job_index + 2, tp, tp_size, true);
+ panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0,
vp, vp_size, true);
return;
}
bool rasterizer_discard = ctx->rasterizer &&
ctx->rasterizer->base.rasterizer_discard;
- unsigned vertex = panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0,
+ unsigned vertex = panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0,
vp, vp_size, false);
if (rasterizer_discard)
return;
- panfrost_new_job(batch, JOB_TYPE_TILER, false, vertex, tp, tp_size,
+ panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, vertex, tp, tp_size,
false);
}
0, 0,
};
- return panfrost_upload_transient(batch, locations, 96 * sizeof(uint16_t));
+ return panfrost_pool_upload(&batch->pool, locations, 96 * sizeof(uint16_t));
}
projects / mesa.git / blobdiff