meta->sampler_count = ctx->sampler_count[st];
if (dev->quirks & IS_BIFROST) {
- meta->bifrost1.unk1 = 0x800200;
+ if (st == PIPE_SHADER_VERTEX)
+ meta->bifrost1.unk1 = 0x800000;
+ else {
+ /* First clause ATEST |= 0x4000000.
+ * Less than 32 regs |= 0x200 */
+ meta->bifrost1.unk1 = 0x958020;
+ }
+
meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
- meta->bifrost2.preload_regs = 0xC0;
+ if (st == PIPE_SHADER_VERTEX)
+ meta->bifrost2.preload_regs = 0xC0;
+ else
+ meta->bifrost2.preload_regs = 0x1;
meta->bifrost2.uniform_count = MIN2(ss->uniform_count,
ss->uniform_cutoff);
} else {
meta->midgard1.flags_lo = 0x220;
meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
}
-
}
static unsigned
hw->max_lod = hw->min_lod + 1;
}
+void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso,
+ struct bifrost_sampler_descriptor *hw)
+{
+ *hw = (struct bifrost_sampler_descriptor) {
+ .unk1 = 0x1,
+ .wrap_s = translate_tex_wrap(cso->wrap_s),
+ .wrap_t = translate_tex_wrap(cso->wrap_t),
+ .wrap_r = translate_tex_wrap(cso->wrap_r),
+ .unk8 = 0x8,
+ .min_filter = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST,
+ .norm_coords = cso->normalized_coords,
+ .mip_filter = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR,
+ .mag_filter = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR,
+ .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */
+ .max_lod = FIXED_16(cso->max_lod, false),
+ };
+
+ /* If necessary, we disable mipmapping in the sampler descriptor by
+ * clamping the LOD as tight as possible (from 0 to epsilon,
+ * essentially -- remember these are fixed point numbers, so
+ * epsilon=1/256) */
+
+ if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
+ hw->max_lod = hw->min_lod + 1;
+}
+
static void
panfrost_make_stencil_state(const struct pipe_stencil_state *in,
struct mali_stencil_test *out)
static void
panfrost_frag_meta_blend_update(struct panfrost_context *ctx,
struct mali_shader_meta *fragmeta,
- struct midgard_blend_rt *rts)
+ void *rts)
{
const struct panfrost_device *dev = pan_device(ctx->base.screen);
/* If there is a blend shader, work registers are shared. XXX: opt */
- for (unsigned c = 0; c < rt_count; ++c) {
- if (blend[c].is_shader)
- fragmeta->midgard1.work_count = 16;
+ if (!(dev->quirks & IS_BIFROST)) {
+ for (unsigned c = 0; c < rt_count; ++c) {
+ if (blend[c].is_shader)
+ fragmeta->midgard1.work_count = 16;
+ }
}
/* Even on MFBD, the shader descriptor gets blend shaders. It's *also*
/* Additional blend descriptor tacked on for jobs using MFBD */
for (unsigned i = 0; i < rt_count; ++i) {
- rts[i].flags = 0x200;
+ if (dev->quirks & IS_BIFROST) {
+ struct bifrost_blend_rt *brts = rts;
+ struct panfrost_shader_state *fs;
+ fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
+
+ brts[i].flags = 0x200;
+ if (blend[i].is_shader) {
+ /* The blend shader's address needs to be at
+ * the same top 32 bit as the fragment shader.
+ * TODO: Ensure that's always the case.
+ */
+ assert((blend[i].shader.gpu & (0xffffffffull << 32)) ==
+ (fs->bo->gpu & (0xffffffffull << 32)));
+ brts[i].shader = blend[i].shader.gpu;
+ brts[i].unk2 = 0x0;
+ } else {
+ enum pipe_format format = ctx->pipe_framebuffer.cbufs[i]->format;
+ const struct util_format_description *format_desc;
+ format_desc = util_format_description(format);
+
+ brts[i].equation = *blend[i].equation.equation;
+
+ /* TODO: this is a bit more complicated */
+ brts[i].constant = blend[i].equation.constant;
+
+ brts[i].format = panfrost_format_to_bifrost_blend(format_desc);
+ brts[i].unk2 = 0x19;
+
+ brts[i].shader_type = fs->blend_types[i];
+ }
+ } else {
+ struct midgard_blend_rt *mrts = rts;
- bool is_srgb = (ctx->pipe_framebuffer.nr_cbufs > i) &&
- (ctx->pipe_framebuffer.cbufs[i]) &&
- util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format);
+ mrts[i].flags = 0x200;
- SET_BIT(rts[i].flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader);
- SET_BIT(rts[i].flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending);
- SET_BIT(rts[i].flags, MALI_BLEND_SRGB, is_srgb);
- SET_BIT(rts[i].flags, MALI_BLEND_NO_DITHER, !ctx->blend->base.dither);
+ bool is_srgb = (ctx->pipe_framebuffer.nr_cbufs > i) &&
+ (ctx->pipe_framebuffer.cbufs[i]) &&
+ util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format);
- if (blend[i].is_shader) {
- rts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag;
- } else {
- rts[i].blend.equation = *blend[i].equation.equation;
- rts[i].blend.constant = blend[i].equation.constant;
+ SET_BIT(mrts[i].flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader);
+ SET_BIT(mrts[i].flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending);
+ SET_BIT(mrts[i].flags, MALI_BLEND_SRGB, is_srgb);
+ SET_BIT(mrts[i].flags, MALI_BLEND_NO_DITHER, !ctx->blend->base.dither);
+
+ if (blend[i].is_shader) {
+ mrts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag;
+ } else {
+ mrts[i].blend.equation = *blend[i].equation.equation;
+ mrts[i].blend.constant = blend[i].equation.constant;
+ }
}
}
}
static void
panfrost_frag_shader_meta_init(struct panfrost_context *ctx,
struct mali_shader_meta *fragmeta,
- struct midgard_blend_rt *rts)
+ void *rts)
{
const struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_shader_state *fs;
SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD);
- /* Depending on whether it's legal to in the given shader, we try to
- * enable early-z testing (or forward-pixel kill?) */
+ if (dev->quirks & IS_BIFROST) {
+ /* TODO */
+ } else {
+ /* Depending on whether it's legal to in the given shader, we try to
+ * enable early-z testing (or forward-pixel kill?) */
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z,
- !fs->can_discard && !fs->writes_depth);
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z,
+ !fs->can_discard && !fs->writes_depth);
- /* Add the writes Z/S flags if needed. */
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth);
- SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil);
+ /* Add the writes Z/S flags if needed. */
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth);
+ SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil);
- /* Any time texturing is used, derivatives are implicitly calculated,
- * so we need to enable helper invocations */
+ /* Any time texturing is used, derivatives are implicitly calculated,
+ * so we need to enable helper invocations */
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS,
- fs->helper_invocations);
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS,
+ fs->helper_invocations);
- /* CAN_DISCARD should be set if the fragment shader possibly contains a
- * 'discard' instruction. It is likely this is related to optimizations
- * related to forward-pixel kill, as per "Mali Performance 3: Is
- * EGL_BUFFER_PRESERVED a good thing?" by Peter Harris */
+ /* CAN_DISCARD should be set if the fragment shader possibly contains a
+ * 'discard' instruction. It is likely this is related to optimizations
+ * related to forward-pixel kill, as per "Mali Performance 3: Is
+ * EGL_BUFFER_PRESERVED a good thing?" by Peter Harris */
- SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, fs->can_discard);
- SET_BIT(fragmeta->midgard1.flags_lo, 0x400, fs->can_discard);
+ SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, fs->can_discard);
+ SET_BIT(fragmeta->midgard1.flags_lo, 0x400, fs->can_discard);
+ }
panfrost_frag_meta_rasterizer_update(ctx, fragmeta);
panfrost_frag_meta_zsa_update(ctx, fragmeta);
struct panfrost_device *dev = pan_device(ctx->base.screen);
unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1);
size_t desc_size = sizeof(meta);
- struct midgard_blend_rt rts[4];
+ void *rts = NULL;
struct panfrost_transfer xfer;
+ unsigned rt_size;
- assert(rt_count <= ARRAY_SIZE(rts));
+ if (dev->quirks & MIDGARD_SFBD)
+ rt_size = 0;
+ else if (dev->quirks & IS_BIFROST)
+ rt_size = sizeof(struct bifrost_blend_rt);
+ else
+ rt_size = sizeof(struct midgard_blend_rt);
- panfrost_frag_shader_meta_init(ctx, &meta, rts);
+ desc_size += rt_size * rt_count;
- if (!(dev->quirks & MIDGARD_SFBD))
- desc_size += sizeof(*rts) * rt_count;
+ if (rt_size)
+ rts = rzalloc_size(ctx, rt_size * rt_count);
+
+ panfrost_frag_shader_meta_init(ctx, &meta, rts);
xfer = panfrost_allocate_transient(batch, desc_size);
memcpy(xfer.cpu, &meta, sizeof(meta));
- memcpy(xfer.cpu + sizeof(meta), rts, sizeof(*rts) * rt_count);
+ memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count);
+
+ if (rt_size)
+ ralloc_free(rts);
shader_ptr = xfer.gpu;
} else {
PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
panfrost_bo_access_for_stage(st));
- panfrost_batch_add_bo(batch, view->bo,
+ panfrost_batch_add_bo(batch, view->midgard_bo,
PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
panfrost_bo_access_for_stage(st));
- return view->bo->gpu;
+ return view->midgard_bo->gpu;
}
void
struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_context *ctx = batch->ctx;
+ struct panfrost_device *device = pan_device(ctx->base.screen);
if (!ctx->sampler_view_count[stage])
return;
- uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
+ if (device->quirks & IS_BIFROST) {
+ struct bifrost_texture_descriptor *descriptors;
+
+ descriptors = malloc(sizeof(struct bifrost_texture_descriptor) *
+ ctx->sampler_view_count[stage]);
+
+ for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) {
+ struct panfrost_sampler_view *view = ctx->sampler_views[stage][i];
+ struct pipe_sampler_view *pview = &view->base;
+ struct panfrost_resource *rsrc = pan_resource(pview->texture);
+
+ /* Add the BOs to the job so they are retained until the job is done. */
- for (int i = 0; i < ctx->sampler_view_count[stage]; ++i)
- trampolines[i] = panfrost_get_tex_desc(batch, stage,
- ctx->sampler_views[stage][i]);
+ panfrost_batch_add_bo(batch, rsrc->bo,
+ PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
+ panfrost_bo_access_for_stage(stage));
+
+ panfrost_batch_add_bo(batch, view->bifrost_bo,
+ PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
+ panfrost_bo_access_for_stage(stage));
+
+ memcpy(&descriptors[i], view->bifrost_descriptor, sizeof(*view->bifrost_descriptor));
+ }
- postfix->texture_trampoline = panfrost_upload_transient(batch,
- trampolines,
- sizeof(uint64_t) *
- ctx->sampler_view_count[stage]);
+ postfix->textures = panfrost_upload_transient(batch,
+ descriptors,
+ sizeof(struct bifrost_texture_descriptor) *
+ ctx->sampler_view_count[stage]);
+
+ free(descriptors);
+ } else {
+ uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
+
+ for (int i = 0; i < ctx->sampler_view_count[stage]; ++i)
+ trampolines[i] = panfrost_get_tex_desc(batch, stage,
+ ctx->sampler_views[stage][i]);
+
+ postfix->textures = panfrost_upload_transient(batch,
+ trampolines,
+ sizeof(uint64_t) *
+ ctx->sampler_view_count[stage]);
+ }
}
void
struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_context *ctx = batch->ctx;
+ struct panfrost_device *device = pan_device(ctx->base.screen);
if (!ctx->sampler_count[stage])
return;
- size_t desc_size = sizeof(struct mali_sampler_descriptor);
- size_t transfer_size = desc_size * ctx->sampler_count[stage];
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
- transfer_size);
- struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *)transfer.cpu;
+ if (device->quirks & IS_BIFROST) {
+ size_t desc_size = sizeof(struct bifrost_sampler_descriptor);
+ size_t transfer_size = desc_size * ctx->sampler_count[stage];
+ struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
+ transfer_size);
+ struct bifrost_sampler_descriptor *desc = (struct bifrost_sampler_descriptor *)transfer.cpu;
+
+ for (int i = 0; i < ctx->sampler_count[stage]; ++i)
+ desc[i] = ctx->samplers[stage][i]->bifrost_hw;
+
+ postfix->sampler_descriptor = transfer.gpu;
+ } else {
+ size_t desc_size = sizeof(struct mali_sampler_descriptor);
+ size_t transfer_size = desc_size * ctx->sampler_count[stage];
+ struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
+ transfer_size);
+ struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *)transfer.cpu;
- for (int i = 0; i < ctx->sampler_count[stage]; ++i)
- desc[i] = ctx->samplers[stage][i]->hw;
+ for (int i = 0; i < ctx->sampler_count[stage]; ++i)
+ desc[i] = ctx->samplers[stage][i]->midgard_hw;
- postfix->sampler_descriptor = transfer.gpu;
+ postfix->sampler_descriptor = transfer.gpu;
+ }
}
void
varyings[gl_FragCoord].elements = MALI_VARYING_FRAG_COORD;
struct panfrost_device *device = pan_device(ctx->base.screen);
- assert(!(device->quirks & IS_BIFROST) || !(reads_point_coord || fs->reads_face || fs->reads_frag_coord));
+ assert(!(device->quirks & IS_BIFROST) || !(reads_point_coord));
/* Let's go ahead and link varying meta to the buffer in question, now
* that that information is available. VARYING_SLOT_POS is mapped to
/* Set the type appropriately. TODO: Integer varyings XXX */
assert(o->stream == 0);
ovs[i].format = pan_xfb_format(o->num_components);
- ovs[i].swizzle = panfrost_get_default_swizzle(o->num_components);
+
+ if (device->quirks & HAS_SWIZZLES)
+ ovs[i].swizzle = panfrost_get_default_swizzle(o->num_components);
+ else
+ ovs[i].swizzle = panfrost_bifrost_swizzle(o->num_components);
/* Link to the fragment */
signed fs_idx = -1;
projects / mesa.git / blobdiff