#include "panfrost-quirks.h"
-#include "pan_allocate.h"
+#include "pan_pool.h"
#include "pan_bo.h"
#include "pan_cmdstream.h"
#include "pan_context.h"
.scratchpad = panfrost_batch_get_scratchpad(batch, shift, dev->thread_tls_alloc, dev->core_count)->gpu,
.shared_workgroup_count = ~0,
};
- postfix->shared_memory = panfrost_upload_transient(batch, &shared, sizeof(shared));
+ postfix->shared_memory = panfrost_pool_upload(&batch->pool, &shared, sizeof(shared));
}
static void
panfrost_vt_attach_framebuffer(struct panfrost_context *ctx,
struct mali_vertex_tiler_postfix *postfix)
{
- struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
-
- /* If we haven't, reserve space for the framebuffer */
-
- if (!batch->framebuffer.gpu) {
- unsigned size = (dev->quirks & MIDGARD_SFBD) ?
- sizeof(struct mali_single_framebuffer) :
- sizeof(struct mali_framebuffer);
-
- batch->framebuffer = panfrost_allocate_transient(batch, size);
-
- /* Tag the pointer */
- if (!(dev->quirks & MIDGARD_SFBD))
- batch->framebuffer.gpu |= MALI_MFBD;
- }
-
- postfix->shared_memory = batch->framebuffer.gpu;
+ postfix->shared_memory = panfrost_batch_reserve_framebuffer(batch);
}
static void
struct mali_vertex_tiler_postfix *postfix)
{
SET_BIT(postfix->gl_enables, MALI_OCCLUSION_QUERY, ctx->occlusion_query);
- if (ctx->occlusion_query)
+ if (ctx->occlusion_query) {
postfix->occlusion_counter = ctx->occlusion_query->bo->gpu;
- else
+ panfrost_batch_add_bo(ctx->batch, ctx->occlusion_query->bo,
+ PAN_BO_ACCESS_SHARED |
+ PAN_BO_ACCESS_RW |
+ PAN_BO_ACCESS_FRAGMENT);
+ } else {
postfix->occlusion_counter = 0;
+ }
}
void
} else {
/* Otherwise, we need to upload to transient memory */
const uint8_t *ibuf8 = (const uint8_t *) info->index.user;
- out = panfrost_upload_transient(batch, ibuf8 + offset,
+ out = panfrost_pool_upload(&batch->pool, ibuf8 + offset,
info->count *
info->index_size);
}
.wrap_s = translate_tex_wrap(cso->wrap_s),
.wrap_t = translate_tex_wrap(cso->wrap_t),
.wrap_r = translate_tex_wrap(cso->wrap_r),
- .compare_func = panfrost_flip_compare_func(func),
+ .compare_func = cso->compare_mode ?
+ panfrost_flip_compare_func(func) :
+ MALI_FUNC_NEVER,
.border_color = {
cso->border_color.f[0],
cso->border_color.f[1],
fragmeta->depth_factor = 0.0f;
SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, false);
SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, false);
+ SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, true);
+ SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, true);
return;
}
- bool msaa = ctx->rasterizer->base.multisample;
+ struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
+
+ bool msaa = rast->multisample;
/* TODO: Sample size */
SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa);
SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa);
- fragmeta->depth_units = ctx->rasterizer->base.offset_units * 2.0f;
- fragmeta->depth_factor = ctx->rasterizer->base.offset_scale;
+
+ struct panfrost_shader_state *fs;
+ fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
+
+ /* EXT_shader_framebuffer_fetch requires the shader to be run
+ * per-sample when outputs are read. */
+ bool per_sample = ctx->min_samples > 1 || fs->outputs_read;
+ SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample);
+
+ fragmeta->depth_units = rast->offset_units * 2.0f;
+ fragmeta->depth_factor = rast->offset_scale;
/* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
- SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A,
- ctx->rasterizer->base.offset_tri);
- SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B,
- ctx->rasterizer->base.offset_tri);
+ SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri);
+ SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri);
+
+ SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near);
+ SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far);
}
static void
struct mali_shader_meta *fragmeta,
void *rts)
{
+ struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
const struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_shader_state *fs;
fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
(dev->quirks & MIDGARD_SFBD) && ctx->blend &&
!ctx->blend->base.dither);
+ SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE,
+ ctx->blend->base.alpha_to_coverage);
+
/* Get blending setup */
unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1);
SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD,
!blend[0].no_blending || fs->can_discard);
+
+ batch->draws |= PIPE_CLEAR_COLOR0;
return;
}
if (ctx->pipe_framebuffer.nr_cbufs > i && !blend[i].no_colour) {
flags = 0x200;
+ batch->draws |= (PIPE_CLEAR_COLOR0 << i);
bool is_srgb = (ctx->pipe_framebuffer.nr_cbufs > i) &&
(ctx->pipe_framebuffer.cbufs[i]) &&
fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
- fragmeta->alpha_coverage = ~MALI_ALPHA_COVERAGE(0.000000);
- fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x3010;
+ bool msaa = ctx->rasterizer && ctx->rasterizer->base.multisample;
+ fragmeta->coverage_mask = (msaa ? ctx->sample_mask : ~0) & 0xF;
+
+ fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10;
fragmeta->unknown2_4 = 0x4e0;
/* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this
SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z,
!fs->can_discard && !fs->writes_global &&
- !fs->writes_depth && !fs->writes_stencil);
+ !fs->writes_depth && !fs->writes_stencil &&
+ !ctx->blend->base.alpha_to_coverage);
/* Add the writes Z/S flags if needed. */
SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth);
SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS,
fs->helper_invocations);
+ /* If discard is enabled, which bit we set to convey this
+ * depends on if depth/stencil is used for the draw or not.
+ * Just one of depth OR stencil is enough to trigger this. */
+
const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil;
+ bool zs_enabled = fs->writes_depth || fs->writes_stencil;
- bool depth_enabled = fs->writes_depth ||
- (zsa && zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS);
+ if (zsa) {
+ zs_enabled |= (zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS);
+ zs_enabled |= zsa->stencil[0].enabled;
+ }
- SET_BIT(fragmeta->midgard1.flags_lo, 0x400, !depth_enabled && fs->can_discard);
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, depth_enabled && fs->can_discard);
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER,
+ fs->outputs_read || (!zs_enabled && fs->can_discard));
+ SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard);
}
panfrost_frag_meta_rasterizer_update(ctx, fragmeta);
panfrost_frag_shader_meta_init(ctx, &meta, rts);
- xfer = panfrost_allocate_transient(batch, desc_size);
+ xfer = panfrost_pool_alloc(&batch->pool, desc_size);
memcpy(xfer.cpu, &meta, sizeof(meta));
memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count);
shader_ptr = xfer.gpu;
} else {
- shader_ptr = panfrost_upload_transient(batch, &meta,
+ shader_ptr = panfrost_pool_upload(&batch->pool, &meta,
sizeof(meta));
}
mvp->viewport0[1] = miny;
mvp->viewport1[1] = MALI_POSITIVE(maxy);
- mvp->clip_minz = minz;
- mvp->clip_maxz = maxz;
+ bool clip_near = true;
+ bool clip_far = true;
+
+ if (ctx->rasterizer) {
+ clip_near = ctx->rasterizer->base.depth_clip_near;
+ clip_far = ctx->rasterizer->base.depth_clip_far;
+ }
+
+ mvp->clip_minz = clip_near ? minz : -INFINITY;
+ mvp->clip_maxz = clip_far ? maxz : INFINITY;
}
void
mvp.viewport1[0] + 1,
mvp.viewport1[1] + 1);
- tiler_postfix->viewport = panfrost_upload_transient(batch, &mvp,
+ tiler_postfix->viewport = panfrost_pool_upload(&batch->pool, &mvp,
sizeof(mvp));
}
* PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
return rsrc->bo->gpu + cb->buffer_offset;
} else if (cb->user_buffer) {
- return panfrost_upload_transient(batch,
+ return panfrost_pool_upload(&batch->pool,
cb->user_buffer +
cb->buffer_offset,
cb->buffer_size);
size_t sys_size = sizeof(float) * 4 * ss->sysval_count;
size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0;
size_t size = sys_size + uniform_size;
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
+ struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool,
size);
/* Upload sysvals requested by the shader */
ubos[ubo] = MALI_MAKE_UBO(aligned / bytes_per_field, gpu);
}
- mali_ptr ubufs = panfrost_upload_transient(batch, ubos, sz);
+ mali_ptr ubufs = panfrost_pool_upload(&batch->pool, ubos, sz);
postfix->uniforms = transfer.gpu;
postfix->uniform_buffers = ubufs;
.shared_shift = util_logbase2(single_size) - 1
};
- vtp->postfix.shared_memory = panfrost_upload_transient(batch, &shared,
+ vtp->postfix.shared_memory = panfrost_pool_upload(&batch->pool, &shared,
sizeof(shared));
}
struct pipe_context *pctx)
{
struct panfrost_resource *rsrc = pan_resource(view->base.texture);
- if (view->layout != rsrc->layout) {
+ if (view->texture_bo != rsrc->bo->gpu ||
+ view->modifier != rsrc->modifier) {
panfrost_bo_unreference(view->bo);
panfrost_create_sampler_view_bo(view, pctx, &rsrc->base);
}
struct panfrost_sampler_view *view = ctx->sampler_views[stage][i];
struct pipe_sampler_view *pview = &view->base;
struct panfrost_resource *rsrc = pan_resource(pview->texture);
+ panfrost_update_sampler_view(view, &ctx->base);
/* Add the BOs to the job so they are retained until the job is done. */
memcpy(&descriptors[i], view->bifrost_descriptor, sizeof(*view->bifrost_descriptor));
}
- postfix->textures = panfrost_upload_transient(batch,
+ postfix->textures = panfrost_pool_upload(&batch->pool,
descriptors,
sizeof(struct bifrost_texture_descriptor) *
ctx->sampler_view_count[stage]);
trampolines[i] = panfrost_get_tex_desc(batch, stage, view);
}
- postfix->textures = panfrost_upload_transient(batch,
+ postfix->textures = panfrost_pool_upload(&batch->pool,
trampolines,
sizeof(uint64_t) *
ctx->sampler_view_count[stage]);
if (device->quirks & IS_BIFROST) {
size_t desc_size = sizeof(struct bifrost_sampler_descriptor);
size_t transfer_size = desc_size * ctx->sampler_count[stage];
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
+ struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool,
transfer_size);
struct bifrost_sampler_descriptor *desc = (struct bifrost_sampler_descriptor *)transfer.cpu;
} else {
size_t desc_size = sizeof(struct mali_sampler_descriptor);
size_t transfer_size = desc_size * ctx->sampler_count[stage];
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
+ struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool,
transfer_size);
struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *)transfer.cpu;
struct panfrost_vertex_state *so = ctx->vertex;
panfrost_vertex_state_upd_attr_offs(ctx, vertex_postfix);
- vertex_postfix->attribute_meta = panfrost_upload_transient(batch, so->hw,
+ vertex_postfix->attribute_meta = panfrost_pool_upload(&batch->pool, so->hw,
sizeof(*so->hw) *
PAN_MAX_ATTRIBUTE);
}
/* Upload whatever we emitted and go */
- vertex_postfix->attributes = panfrost_upload_transient(batch, attrs,
+ vertex_postfix->attributes = panfrost_pool_upload(&batch->pool, attrs,
k * sizeof(*attrs));
}
slot->size = stride * count;
slot->shift = slot->extra_flags = 0;
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
+ struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool,
slot->size);
slot->elements = transfer.gpu | MALI_ATTR_LINEAR;
vs_size = sizeof(struct mali_attr_meta) * vs->varying_count;
fs_size = sizeof(struct mali_attr_meta) * fs->varying_count;
- struct panfrost_transfer trans = panfrost_allocate_transient(batch,
+ struct panfrost_transfer trans = panfrost_pool_alloc(&batch->pool,
vs_size +
fs_size);
}
unsigned xfb_base = pan_xfb_base(present);
- struct panfrost_transfer T = panfrost_allocate_transient(batch,
+ struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool,
sizeof(union mali_attr) * (xfb_base + ctx->streamout.num_targets));
union mali_attr *varyings = (union mali_attr *) T.cpu;
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_device *device = pan_device(ctx->base.screen);
- bool wallpapering = ctx->wallpaper_batch && batch->tiler_dep;
+ bool wallpapering = ctx->wallpaper_batch && batch->scoreboard.tiler_dep;
struct bifrost_payload_vertex bifrost_vertex = {0,};
struct bifrost_payload_tiler bifrost_tiler = {0,};
struct midgard_payload_vertex_tiler midgard_vertex = {0,};
if (wallpapering) {
/* Inject in reverse order, with "predicted" job indices.
* THIS IS A HACK XXX */
- panfrost_new_job(batch, JOB_TYPE_TILER, false,
- batch->job_index + 2, tp, tp_size, true);
- panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0,
+ panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false,
+ batch->scoreboard.job_index + 2, tp, tp_size, true);
+ panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0,
vp, vp_size, true);
return;
}
bool rasterizer_discard = ctx->rasterizer &&
ctx->rasterizer->base.rasterizer_discard;
- unsigned vertex = panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0,
+ unsigned vertex = panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0,
vp, vp_size, false);
if (rasterizer_discard)
return;
- panfrost_new_job(batch, JOB_TYPE_TILER, false, vertex, tp, tp_size,
+ panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, vertex, tp, tp_size,
false);
}
0, 0,
};
- return panfrost_upload_transient(batch, locations, 96 * sizeof(uint16_t));
+ return panfrost_pool_upload(&batch->pool, locations, 96 * sizeof(uint16_t));
}
projects / mesa.git / blobdiff