PAN_BO_ACCESS_VERTEX_TILER;
}
-static void
-panfrost_vt_emit_shared_memory(struct panfrost_context *ctx,
- struct mali_vertex_tiler_postfix *postfix)
+static mali_ptr
+panfrost_vt_emit_shared_memory(struct panfrost_batch *batch)
{
- struct panfrost_device *dev = pan_device(ctx->base.screen);
- struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
+ struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
struct mali_shared_memory shared = {
.shared_workgroup_count = ~0,
shared.scratchpad = stack->gpu;
}
- postfix->shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared, sizeof(shared), 64);
-}
-
-static void
-panfrost_vt_attach_framebuffer(struct panfrost_context *ctx,
- struct mali_vertex_tiler_postfix *postfix)
-{
- struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
- postfix->shared_memory = panfrost_batch_reserve_framebuffer(batch);
-}
-
-static void
-panfrost_vt_update_rasterizer(struct panfrost_rasterizer *rasterizer,
- struct mali_vertex_tiler_prefix *prefix,
- struct mali_vertex_tiler_postfix *postfix)
-{
- postfix->gl_enables |= 0x7;
- SET_BIT(postfix->gl_enables, MALI_FRONT_CCW_TOP,
- rasterizer->base.front_ccw);
- SET_BIT(postfix->gl_enables, MALI_CULL_FACE_FRONT,
- (rasterizer->base.cull_face & PIPE_FACE_FRONT));
- SET_BIT(postfix->gl_enables, MALI_CULL_FACE_BACK,
- (rasterizer->base.cull_face & PIPE_FACE_BACK));
- SET_BIT(prefix->unknown_draw, MALI_DRAW_FLATSHADE_FIRST,
- rasterizer->base.flatshade_first);
+ return panfrost_pool_upload_aligned(&batch->pool, &shared, sizeof(shared), 64);
}
void
}
}
-static void
-panfrost_vt_update_occlusion_query(struct panfrost_context *ctx,
- struct mali_vertex_tiler_postfix *postfix)
-{
- SET_BIT(postfix->gl_enables, MALI_OCCLUSION_QUERY, ctx->occlusion_query);
- if (ctx->occlusion_query) {
- postfix->occlusion_counter = ctx->occlusion_query->bo->gpu;
- panfrost_batch_add_bo(ctx->batch, ctx->occlusion_query->bo,
- PAN_BO_ACCESS_SHARED |
- PAN_BO_ACCESS_RW |
- PAN_BO_ACCESS_FRAGMENT);
- } else {
- postfix->occlusion_counter = 0;
- }
-}
-
void
panfrost_vt_init(struct panfrost_context *ctx,
enum pipe_shader_type stage,
struct mali_vertex_tiler_postfix *postfix)
{
struct panfrost_device *device = pan_device(ctx->base.screen);
+ struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
if (!ctx->shader[stage])
return;
if (device->quirks & IS_BIFROST) {
postfix->gl_enables = 0x2;
- panfrost_vt_emit_shared_memory(ctx, postfix);
+ postfix->shared_memory = panfrost_vt_emit_shared_memory(batch);
} else {
postfix->gl_enables = 0x6;
- panfrost_vt_attach_framebuffer(ctx, postfix);
+ postfix->shared_memory = panfrost_batch_reserve_framebuffer(batch);
}
if (stage == PIPE_SHADER_FRAGMENT) {
- panfrost_vt_update_occlusion_query(ctx, postfix);
- panfrost_vt_update_rasterizer(ctx->rasterizer, prefix, postfix);
+ if (ctx->occlusion_query) {
+ postfix->gl_enables |= MALI_OCCLUSION_QUERY;
+ postfix->occlusion_counter = ctx->occlusion_query->bo->gpu;
+ panfrost_batch_add_bo(ctx->batch, ctx->occlusion_query->bo,
+ PAN_BO_ACCESS_SHARED |
+ PAN_BO_ACCESS_RW |
+ PAN_BO_ACCESS_FRAGMENT);
+ }
+
+ postfix->gl_enables |= 0x7;
+ struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
+ SET_BIT(postfix->gl_enables, MALI_FRONT_CCW_TOP,
+ rast->front_ccw);
+ SET_BIT(postfix->gl_enables, MALI_CULL_FACE_FRONT,
+ (rast->cull_face & PIPE_FACE_FRONT));
+ SET_BIT(postfix->gl_enables, MALI_CULL_FACE_BACK,
+ (rast->cull_face & PIPE_FACE_BACK));
+ SET_BIT(prefix->unknown_draw, MALI_DRAW_FLATSHADE_FIRST,
+ rast->flatshade_first);
}
}
}
tiler_prefix->unknown_draw = draw_flags;
+ ctx->offset_start = vertex_postfix->offset_start;
/* Encode the padded vertex count */
}
}
-static void
-panfrost_emit_compute_shader(struct panfrost_context *ctx,
- enum pipe_shader_type st,
- struct mali_shader_meta *meta)
-{
- const struct panfrost_device *dev = pan_device(ctx->base.screen);
- struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st);
-
- memset(meta, 0, sizeof(*meta));
- memcpy(&meta->shader, &ss->shader, sizeof(ss->shader));
-
- if (dev->quirks & IS_BIFROST) {
- struct mali_bifrost_properties_packed prop;
- struct mali_preload_vertex_packed preload;
-
- pan_pack(&prop, BIFROST_PROPERTIES, cfg) {
- cfg.unknown = 0x800000; /* XXX */
- cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st);
- }
-
- /* TODO: True compute shaders */
- pan_pack(&preload, PRELOAD_VERTEX, cfg) {
- cfg.uniform_count = ss->uniform_count;
- cfg.vertex_id = true;
- cfg.instance_id = true;
- }
-
- memcpy(&meta->bifrost_props, &prop, sizeof(prop));
- memcpy(&meta->bifrost_preload, &preload, sizeof(preload));
- } else {
- struct mali_midgard_properties_packed prop;
-
- pan_pack(&prop, MIDGARD_PROPERTIES, cfg) {
- cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st);
- cfg.uniform_count = ss->uniform_count;
- cfg.work_register_count = ss->work_reg_count;
- cfg.writes_globals = ss->writes_global;
- cfg.suppress_inf_nan = true; /* XXX */
- }
-
- memcpy(&meta->midgard_props, &prop, sizeof(prop));
- }
-}
-
static unsigned
translate_tex_wrap(enum pipe_tex_wrap w)
{
unsigned rt_count = batch->key.nr_cbufs;
struct bifrost_blend_rt *brts = rts;
- struct midgard_blend_rt *mrts = rts;
- /* Disable blending for depth-only on Bifrost */
+ /* Disable blending for depth-only */
- if (rt_count == 0 && dev->quirks & IS_BIFROST)
- brts[0].unk2 = 0x3;
+ if (rt_count == 0) {
+ if (dev->quirks & IS_BIFROST) {
+ memset(brts, 0, sizeof(*brts));
+ brts[0].unk2 = 0x3;
+ } else {
+ pan_pack(rts, MIDGARD_BLEND_OPAQUE, cfg) {
+ cfg.equation = 0xf0122122; /* Replace */
+ }
+ }
+ }
for (unsigned i = 0; i < rt_count; ++i) {
- unsigned flags = 0;
+ struct mali_blend_flags_packed flags = {};
pan_pack(&flags, BLEND_FLAGS, cfg) {
if (blend[i].no_colour) {
}
if (dev->quirks & IS_BIFROST) {
- brts[i].flags = flags;
+ memset(brts + i, 0, sizeof(brts[i]));
+ brts[i].flags = flags.opaque[0];
if (blend[i].is_shader) {
/* The blend shader's address needs to be at
brts[i].shader_type = fs->blend_types[i];
}
} else {
- memcpy(&mrts[i].flags, &flags, sizeof(flags));
-
- if (blend[i].is_shader) {
- mrts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag;
- } else {
- mrts[i].blend.equation = blend[i].equation.equation;
- mrts[i].blend.constant = blend[i].equation.constant;
+ pan_pack(rts, MIDGARD_BLEND_OPAQUE, cfg) {
+ cfg.flags = flags;
+
+ if (blend[i].is_shader) {
+ cfg.shader = blend[i].shader.gpu | blend[i].shader.first_tag;
+ } else {
+ cfg.equation = blend[i].equation.equation.opaque[0];
+ cfg.constant = blend[i].equation.constant;
+ }
}
- }
- }
-}
-
-static struct mali_shader_packed
-panfrost_pack_shaderless(bool midgard)
-{
- struct mali_shader_packed pack;
- pan_pack(&pack, SHADER, cfg) {
- cfg.shader = midgard ? 0x1 : 0x0;
+ rts += MALI_MIDGARD_BLEND_LENGTH;
+ }
}
-
- return pack;
}
static void
panfrost_emit_frag_shader(struct panfrost_context *ctx,
- struct mali_shader_meta *fragmeta,
+ struct mali_state_packed *fragmeta,
struct panfrost_blend_final *blend)
{
const struct panfrost_device *dev = pan_device(ctx->base.screen);
- struct panfrost_shader_state *fs;
-
- fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
-
+ struct panfrost_shader_state *fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
const struct panfrost_zsa_state *zsa = ctx->depth_stencil;
unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs;
+ bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
- memset(fragmeta, 0, sizeof(*fragmeta));
- memcpy(&fragmeta->shader, &fs->shader, sizeof(fs->shader));
+ /* Built up here */
+ struct mali_shader_packed shader = fs->shader;
+ struct mali_preload_packed preload = fs->preload;
+ uint32_t properties;
+ struct mali_multisample_misc_packed multisample_misc;
+ struct mali_stencil_mask_misc_packed stencil_mask_misc;
+ union midgard_blend sfbd_blend = { 0 };
- if (dev->quirks & IS_BIFROST) {
- struct mali_bifrost_properties_packed prop;
- struct mali_preload_fragment_packed preload;
+ if (!panfrost_fs_required(fs, blend, rt_count)) {
+ if (dev->quirks & IS_BIFROST) {
+ pan_pack(&shader, SHADER, cfg) {}
+ pan_pack(&properties, BIFROST_PROPERTIES, cfg) {
+ cfg.unknown = 0x950020; /* XXX */
+ cfg.early_z_enable = true;
+ }
+
+ preload.opaque[0] = 0;
+ } else {
+ pan_pack(&shader, SHADER, cfg) {
+ cfg.shader = 0x1;
+ }
+
+ pan_pack(&properties, MIDGARD_PROPERTIES, cfg) {
+ cfg.work_register_count = 1;
+ cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
+ cfg.early_z_enable = true;
+ }
+ }
+ } else if (dev->quirks & IS_BIFROST) {
bool no_blend = true;
for (unsigned i = 0; i < rt_count; ++i)
no_blend &= (!blend[i].load_dest | blend[i].no_colour);
- pan_pack(&prop, BIFROST_PROPERTIES, cfg) {
- cfg.unknown = 0x950020; /* XXX */
- cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT);
+ pan_pack(&properties, BIFROST_PROPERTIES, cfg) {
cfg.early_z_enable = !fs->can_discard && !fs->writes_depth && no_blend;
}
- pan_pack(&preload, PRELOAD_FRAGMENT, cfg) {
- cfg.uniform_count = fs->uniform_count;
- cfg.fragment_position = fs->reads_frag_coord;
- }
-
- memcpy(&fragmeta->bifrost_props, &prop, sizeof(prop));
- memcpy(&fragmeta->bifrost_preload, &preload, sizeof(preload));
+ /* Combine with prepacked properties */
+ properties |= fs->properties.opaque[0];
} else {
- struct mali_midgard_properties_packed prop;
-
/* Reasons to disable early-Z from a shader perspective */
bool late_z = fs->can_discard || fs->writes_global ||
fs->writes_depth || fs->writes_stencil;
- /* Reasons to disable early-Z from a CSO perspective */
- bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
-
/* If either depth or stencil is enabled, discard matters */
bool zs_enabled =
(zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) ||
for (unsigned c = 0; c < rt_count; ++c)
has_blend_shader |= blend[c].is_shader;
- pan_pack(&prop, MIDGARD_PROPERTIES, cfg) {
- cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT);
- cfg.uniform_count = fs->uniform_count;
- cfg.work_register_count = fs->work_reg_count;
- cfg.writes_globals = fs->writes_global;
- cfg.suppress_inf_nan = true; /* XXX */
-
+ pan_pack(&properties, MIDGARD_PROPERTIES, cfg) {
/* TODO: Reduce this limit? */
if (has_blend_shader)
- cfg.work_register_count = MAX2(cfg.work_register_count, 8);
-
- cfg.stencil_from_shader = fs->writes_stencil;
- cfg.helper_invocation_enable = fs->helper_invocations;
- cfg.depth_source = fs->writes_depth ?
- MALI_DEPTH_SOURCE_SHADER :
- MALI_DEPTH_SOURCE_FIXED_FUNCTION;
+ cfg.work_register_count = MAX2(fs->work_reg_count, 8);
+ else
+ cfg.work_register_count = fs->work_reg_count;
- /* Depend on other state */
cfg.early_z_enable = !(late_z || alpha_to_coverage);
cfg.reads_tilebuffer = fs->outputs_read || (!zs_enabled && fs->can_discard);
cfg.reads_depth_stencil = zs_enabled && fs->can_discard;
}
- memcpy(&fragmeta->midgard_props, &prop, sizeof(prop));
+ properties |= fs->properties.opaque[0];
}
- bool msaa = rast->multisample;
- fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0;
-
- fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10;
- fragmeta->unknown2_4 = 0x4e0;
-
- /* TODO: Sample size */
- SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa);
- SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa);
-
- /* EXT_shader_framebuffer_fetch requires the shader to be run
- * per-sample when outputs are read. */
- bool per_sample = ctx->min_samples > 1 || fs->outputs_read;
- SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample);
-
- fragmeta->depth_units = rast->offset_units * 2.0f;
- fragmeta->depth_factor = rast->offset_scale;
-
- /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
+ pan_pack(&multisample_misc, MULTISAMPLE_MISC, cfg) {
+ bool msaa = rast->multisample;
+ cfg.multisample_enable = msaa;
+ cfg.sample_mask = (msaa ? ctx->sample_mask : ~0) & 0xFFFF;
- SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri);
- SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri);
+ /* EXT_shader_framebuffer_fetch requires per-sample */
+ bool per_sample = ctx->min_samples > 1 || fs->outputs_read;
+ cfg.evaluate_per_sample = msaa && per_sample;
- SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near);
- SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far);
-
- SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST,
- zsa->base.stencil[0].enabled);
-
- fragmeta->stencil_mask_front = zsa->stencil_mask_front;
- fragmeta->stencil_mask_back = zsa->stencil_mask_back;
-
- /* Bottom bits for stencil ref, exactly one word */
- fragmeta->stencil_front.opaque[0] = zsa->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0];
-
- /* If back-stencil is not enabled, use the front values */
-
- if (zsa->base.stencil[1].enabled)
- fragmeta->stencil_back.opaque[0] = zsa->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1];
- else
- fragmeta->stencil_back = fragmeta->stencil_front;
-
- SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK,
- zsa->base.depth.writemask);
-
- fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
- fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(
- zsa->base.depth.enabled ? zsa->base.depth.func : PIPE_FUNC_ALWAYS));
-
- SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE,
- ctx->blend->base.alpha_to_coverage);
+ if (dev->quirks & MIDGARD_SFBD) {
+ cfg.sfbd_load_destination = blend[0].load_dest;
+ cfg.sfbd_blend_shader = blend[0].is_shader;
+ }
- /* Disable shader execution if we can */
- if (!panfrost_fs_required(fs, blend, rt_count)) {
- struct mali_shader_packed shader =
- panfrost_pack_shaderless(!(dev->quirks & IS_BIFROST));
+ cfg.depth_function = zsa->base.depth.enabled ?
+ panfrost_translate_compare_func(zsa->base.depth.func) :
+ MALI_FUNC_ALWAYS;
- memcpy(&fragmeta->shader, &shader, sizeof(shader));
+ cfg.depth_write_mask = zsa->base.depth.writemask;
+ cfg.near_discard = rast->depth_clip_near;
+ cfg.far_discard = rast->depth_clip_far;
+ cfg.unknown_2 = true;
+ }
- struct mali_midgard_properties_packed prop;
+ pan_pack(&stencil_mask_misc, STENCIL_MASK_MISC, cfg) {
+ cfg.stencil_mask_front = zsa->stencil_mask_front;
+ cfg.stencil_mask_back = zsa->stencil_mask_back;
+ cfg.stencil_enable = zsa->base.stencil[0].enabled;
+ cfg.alpha_to_coverage = alpha_to_coverage;
- if (dev->quirks & IS_BIFROST) {
- pan_pack(&prop, BIFROST_PROPERTIES, cfg) {
- cfg.unknown = 0x950020; /* XXX */
- cfg.early_z_enable = true;
- }
- } else {
- pan_pack(&prop, MIDGARD_PROPERTIES, cfg) {
- cfg.work_register_count = 1;
- cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
- cfg.early_z_enable = true;
- }
+ if (dev->quirks & MIDGARD_SFBD) {
+ cfg.sfbd_write_enable = !blend[0].no_colour;
+ cfg.sfbd_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format);
+ cfg.sfbd_dither_disable = !ctx->blend->base.dither;
}
- memcpy(&fragmeta->midgard_props, &prop, sizeof(prop));
+ cfg.unknown_1 = 0x7;
+ cfg.depth_range_1 = cfg.depth_range_2 = rast->offset_tri;
+ cfg.single_sampled_lines = !rast->multisample;
}
if (dev->quirks & MIDGARD_SFBD) {
- /* When only a single render target platform is used, the blend
- * information is inside the shader meta itself. We additionally
- * need to signal CAN_DISCARD for nontrivial blend modes (so
- * we're able to read back the destination buffer) */
-
- if (blend[0].no_colour)
- return;
-
- fragmeta->unknown2_4 |= MALI_SFBD_ENABLE;
-
- SET_BIT(fragmeta->unknown2_4, MALI_SFBD_SRGB,
- util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format));
-
- SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER,
- blend[0].is_shader);
-
if (blend[0].is_shader) {
- fragmeta->blend.shader = blend[0].shader.gpu |
+ sfbd_blend.shader = blend[0].shader.gpu |
blend[0].shader.first_tag;
} else {
- fragmeta->blend.equation = blend[0].equation.equation;
- fragmeta->blend.constant = blend[0].equation.constant;
+ sfbd_blend.equation = blend[0].equation.equation;
+ sfbd_blend.constant = blend[0].equation.constant;
}
-
- SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD,
- blend[0].load_dest);
-
- SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, !ctx->blend->base.dither);
} else if (!(dev->quirks & IS_BIFROST)) {
/* Bug where MRT-capable hw apparently reads the last blend
* shader from here instead of the usual location? */
if (!blend[rt].is_shader)
continue;
- fragmeta->blend.shader = blend[rt].shader.gpu |
+ sfbd_blend.shader = blend[rt].shader.gpu |
blend[rt].shader.first_tag;
break;
}
}
-}
-void
-panfrost_emit_shader_meta(struct panfrost_batch *batch,
- enum pipe_shader_type st,
- struct mali_vertex_tiler_postfix *postfix)
-{
- struct panfrost_context *ctx = batch->ctx;
- struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st);
+ pan_pack(fragmeta, STATE_OPAQUE, cfg) {
+ cfg.shader = fs->shader;
+ cfg.properties = properties;
+ cfg.depth_units = rast->offset_units * 2.0f;
+ cfg.depth_factor = rast->offset_scale;
+ cfg.multisample_misc = multisample_misc;
+ cfg.stencil_mask_misc = stencil_mask_misc;
- if (!ss) {
- postfix->shader = 0;
- return;
+ cfg.stencil_front = zsa->stencil_front;
+ cfg.stencil_back = zsa->stencil_back;
+
+ /* Bottom bits for stencil ref, exactly one word */
+ bool back_enab = zsa->base.stencil[1].enabled;
+ cfg.stencil_front.opaque[0] |= ctx->stencil_ref.ref_value[0];
+ cfg.stencil_back.opaque[0] |= ctx->stencil_ref.ref_value[back_enab ? 1 : 0];
+
+ if (dev->quirks & IS_BIFROST)
+ cfg.preload = preload;
+ else
+ memcpy(&cfg.sfbd_blend, &sfbd_blend, sizeof(sfbd_blend));
}
+}
- struct mali_shader_meta meta;
+mali_ptr
+panfrost_emit_compute_shader_meta(struct panfrost_batch *batch, enum pipe_shader_type stage)
+{
+ struct panfrost_shader_state *ss = panfrost_get_shader_state(batch->ctx, stage);
- /* Add the shader BO to the batch. */
panfrost_batch_add_bo(batch, ss->bo,
PAN_BO_ACCESS_PRIVATE |
PAN_BO_ACCESS_READ |
- panfrost_bo_access_for_stage(st));
+ PAN_BO_ACCESS_VERTEX_TILER);
- mali_ptr shader_ptr;
-
- if (st == PIPE_SHADER_FRAGMENT) {
- struct panfrost_device *dev = pan_device(ctx->base.screen);
- unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1);
- size_t desc_size = sizeof(meta);
- void *rts = NULL;
- struct panfrost_transfer xfer;
- unsigned rt_size;
-
- if (dev->quirks & MIDGARD_SFBD)
- rt_size = 0;
- else if (dev->quirks & IS_BIFROST)
- rt_size = sizeof(struct bifrost_blend_rt);
- else
- rt_size = sizeof(struct midgard_blend_rt);
-
- desc_size += rt_size * rt_count;
-
- if (rt_size)
- rts = rzalloc_size(ctx, rt_size * rt_count);
+ panfrost_batch_add_bo(batch, pan_resource(ss->upload.rsrc)->bo,
+ PAN_BO_ACCESS_PRIVATE |
+ PAN_BO_ACCESS_READ |
+ PAN_BO_ACCESS_VERTEX_TILER);
- struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS];
+ return pan_resource(ss->upload.rsrc)->bo->gpu + ss->upload.offset;
+}
- for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c)
- blend[c] = panfrost_get_blend_for_context(ctx, c);
+mali_ptr
+panfrost_emit_frag_shader_meta(struct panfrost_batch *batch)
+{
+ struct panfrost_context *ctx = batch->ctx;
+ struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
- panfrost_emit_frag_shader(ctx, &meta, blend);
+ /* Add the shader BO to the batch. */
+ panfrost_batch_add_bo(batch, ss->bo,
+ PAN_BO_ACCESS_PRIVATE |
+ PAN_BO_ACCESS_READ |
+ PAN_BO_ACCESS_FRAGMENT);
- if (!(dev->quirks & MIDGARD_SFBD))
- panfrost_emit_blend(batch, rts, blend);
- else
- batch->draws |= PIPE_CLEAR_COLOR0;
+ struct panfrost_device *dev = pan_device(ctx->base.screen);
+ unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1);
+ struct panfrost_transfer xfer;
+ unsigned rt_size;
+
+ if (dev->quirks & MIDGARD_SFBD)
+ rt_size = 0;
+ else if (dev->quirks & IS_BIFROST)
+ rt_size = sizeof(struct bifrost_blend_rt);
+ else
+ rt_size = sizeof(struct midgard_blend_rt);
- xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, sizeof(meta));
+ unsigned desc_size = MALI_STATE_LENGTH + rt_size * rt_count;
+ xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, MALI_STATE_LENGTH);
- memcpy(xfer.cpu, &meta, sizeof(meta));
- memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count);
+ struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS];
- if (rt_size)
- ralloc_free(rts);
+ for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c)
+ blend[c] = panfrost_get_blend_for_context(ctx, c);
- shader_ptr = xfer.gpu;
- } else {
- panfrost_emit_compute_shader(ctx, st, &meta);
+ panfrost_emit_frag_shader(ctx, (struct mali_state_packed *) xfer.cpu, blend);
- shader_ptr = panfrost_pool_upload(&batch->pool, &meta,
- sizeof(meta));
- }
+ if (!(dev->quirks & MIDGARD_SFBD))
+ panfrost_emit_blend(batch, xfer.cpu + MALI_STATE_LENGTH, blend);
+ else
+ batch->draws |= PIPE_CLEAR_COLOR0;
- postfix->shader = shader_ptr;
+ return xfer.gpu;
}
-void
-panfrost_emit_viewport(struct panfrost_batch *batch,
- struct mali_vertex_tiler_postfix *tiler_postfix)
+mali_ptr
+panfrost_emit_viewport(struct panfrost_batch *batch)
{
struct panfrost_context *ctx = batch->ctx;
const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
cfg.maximum_z = rast->depth_clip_far ? maxz : INFINITY;
}
- tiler_postfix->viewport = T.gpu;
panfrost_batch_union_scissor(batch, minx, miny, maxx, maxy);
+ return T.gpu;
}
static mali_ptr
unreachable("No constant buffer");
}
-void
+mali_ptr
panfrost_emit_const_buf(struct panfrost_batch *batch,
enum pipe_shader_type stage,
- struct mali_vertex_tiler_postfix *postfix)
+ mali_ptr *push_constants)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_shader_variants *all = ctx->shader[stage];
if (!all)
- return;
+ return 0;
struct panfrost_constant_buffer *buf = &ctx->constant_buffer[stage];
}
/* Next up, attach UBOs. UBO #0 is the uniforms we just
- * uploaded */
+ * uploaded, so it's always included. The count is the highest UBO
+ * addressable -- gaps are included. */
- unsigned ubo_count = panfrost_ubo_count(ctx, stage);
- assert(ubo_count >= 1);
+ unsigned ubo_count = 32 - __builtin_clz(buf->enabled_mask | 1);
size_t sz = MALI_UNIFORM_BUFFER_LENGTH * ubo_count;
struct panfrost_transfer ubos =
}
}
- postfix->uniforms = transfer.gpu;
- postfix->uniform_buffers = ubos.gpu;
+ *push_constants = transfer.gpu;
buf->dirty_mask = 0;
+ return ubos.gpu;
}
-void
+mali_ptr
panfrost_emit_shared_memory(struct panfrost_batch *batch,
- const struct pipe_grid_info *info,
- struct midgard_payload_vertex_tiler *vtp)
+ const struct pipe_grid_info *info)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_device *dev = pan_device(ctx->base.screen);
.shared_shift = util_logbase2(single_size) + 1
};
- vtp->postfix.shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared,
- sizeof(shared), 64);
+ return panfrost_pool_upload_aligned(&batch->pool, &shared,
+ sizeof(shared), 64);
}
static mali_ptr
}
}
-void
+mali_ptr
panfrost_emit_texture_descriptors(struct panfrost_batch *batch,
- enum pipe_shader_type stage,
- struct mali_vertex_tiler_postfix *postfix)
+ enum pipe_shader_type stage)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_device *device = pan_device(ctx->base.screen);
if (!ctx->sampler_view_count[stage])
- return;
+ return 0;
if (device->quirks & IS_BIFROST) {
struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool,
panfrost_bo_access_for_stage(stage));
}
- postfix->textures = T.gpu;
+ return T.gpu;
} else {
uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
trampolines[i] = panfrost_get_tex_desc(batch, stage, view);
}
- postfix->textures = panfrost_pool_upload_aligned(&batch->pool,
- trampolines,
- sizeof(uint64_t) *
- ctx->sampler_view_count[stage],
- sizeof(uint64_t));
+ return panfrost_pool_upload_aligned(&batch->pool, trampolines,
+ sizeof(uint64_t) *
+ ctx->sampler_view_count[stage],
+ sizeof(uint64_t));
}
}
-void
+mali_ptr
panfrost_emit_sampler_descriptors(struct panfrost_batch *batch,
- enum pipe_shader_type stage,
- struct mali_vertex_tiler_postfix *postfix)
+ enum pipe_shader_type stage)
{
struct panfrost_context *ctx = batch->ctx;
if (!ctx->sampler_count[stage])
- return;
+ return 0;
size_t desc_size = MALI_BIFROST_SAMPLER_LENGTH;
assert(MALI_BIFROST_SAMPLER_LENGTH == MALI_MIDGARD_SAMPLER_LENGTH);
for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i)
out[i] = ctx->samplers[stage][i]->hw;
- postfix->sampler_descriptor = T.gpu;
+ return T.gpu;
}
-void
+mali_ptr
panfrost_emit_vertex_data(struct panfrost_batch *batch,
- struct mali_vertex_tiler_postfix *vertex_postfix)
+ mali_ptr *buffers)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_vertex_state *so = ctx->vertex;
struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
- unsigned instance_shift = vertex_postfix->instance_shift;
- unsigned instance_odd = vertex_postfix->instance_odd;
-
/* Worst case: everything is NPOT, which is only possible if instancing
* is enabled. Otherwise single record is gauranteed */
- bool could_npot = instance_shift || instance_odd;
-
struct panfrost_transfer S = panfrost_pool_alloc_aligned(&batch->pool,
MALI_ATTRIBUTE_BUFFER_LENGTH * vs->attribute_count *
- (could_npot ? 2 : 1),
+ (ctx->instance_count > 1 ? 2 : 1),
MALI_ATTRIBUTE_BUFFER_LENGTH * 2);
struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool,
if (!divisor || ctx->instance_count <= 1) {
pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) {
- if (ctx->instance_count > 1)
+ if (ctx->instance_count > 1) {
cfg.type = MALI_ATTRIBUTE_TYPE_1D_MODULUS;
+ cfg.divisor = ctx->padded_count;
+ }
cfg.pointer = addr;
cfg.stride = stride;
cfg.size = size;
- cfg.divisor_r = instance_shift;
- cfg.divisor_p = instance_odd;
}
} else if (util_is_power_of_two_or_zero(hw_divisor)) {
pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) {
* addressing modes and now base is 64 aligned.
*/
- unsigned start = vertex_postfix->offset_start;
-
for (unsigned i = 0; i < so->num_elements; ++i) {
unsigned vbi = so->pipe[i].vertex_buffer_index;
struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
/* Also, somewhat obscurely per-instance data needs to be
* offset in response to a delayed start in an indexed draw */
- if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start)
- src_offset -= buf->stride * start;
+ if (so->pipe[i].instance_divisor && ctx->instance_count > 1)
+ src_offset -= buf->stride * ctx->offset_start;
pan_pack(out + i, ATTRIBUTE, cfg) {
cfg.buffer_index = attrib_to_buffer[i];
}
}
- vertex_postfix->attributes = S.gpu;
- vertex_postfix->attribute_meta = T.gpu;
+ *buffers = S.gpu;
+ return T.gpu;
}
static mali_ptr
projects / mesa.git / blobdiff