}
static void
-panfrost_shader_meta_init(struct panfrost_context *ctx,
+panfrost_emit_compute_shader(struct panfrost_context *ctx,
enum pipe_shader_type st,
struct mali_shader_meta *meta)
{
struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st);
memset(meta, 0, sizeof(*meta));
- meta->shader = (ss->bo ? ss->bo->gpu : 0) | ss->first_tag;
+ meta->shader = ss->shader;
meta->attribute_count = ss->attribute_count;
meta->varying_count = ss->varying_count;
meta->texture_count = ctx->sampler_view_count[st];
meta->sampler_count = ctx->sampler_count[st];
if (dev->quirks & IS_BIFROST) {
- if (st == PIPE_SHADER_VERTEX)
- meta->bifrost1.unk1 = 0x800000;
- else {
- /* First clause ATEST |= 0x4000000.
- * Less than 32 regs |= 0x200 */
- meta->bifrost1.unk1 = 0x950020;
- }
+ struct mali_bifrost_properties_packed prop;
- meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
- if (st == PIPE_SHADER_VERTEX)
- meta->bifrost2.preload_regs = 0xC0;
- else {
- meta->bifrost2.preload_regs = 0x1;
- SET_BIT(meta->bifrost2.preload_regs, 0x10, ss->reads_frag_coord);
+ pan_pack(&prop, BIFROST_PROPERTIES, cfg) {
+ cfg.unknown = 0x800000; /* XXX */
+ cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st);
}
- meta->bifrost2.uniform_count = MIN2(ss->uniform_count,
- ss->uniform_cutoff);
- } else {
- meta->midgard1.uniform_count = MIN2(ss->uniform_count,
- ss->uniform_cutoff);
- meta->midgard1.work_count = ss->work_reg_count;
-
- /* TODO: This is not conformant on ES3 */
- meta->midgard1.flags_hi = MALI_SUPPRESS_INF_NAN;
+ memcpy(&meta->bifrost_props, &prop, sizeof(prop));
- meta->midgard1.flags_lo = 0x20;
- meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
+ meta->bifrost2.preload_regs = 0xC0;
+ meta->bifrost2.uniform_count = ss->uniform_count;
+ } else {
+ struct mali_midgard_properties_packed prop;
+
+ pan_pack(&prop, MIDGARD_PROPERTIES, cfg) {
+ cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st);
+ cfg.uniform_count = ss->uniform_count;
+ cfg.work_register_count = ss->work_reg_count;
+ cfg.writes_globals = ss->writes_global;
+ cfg.suppress_inf_nan = true; /* XXX */
+ }
- SET_BIT(meta->midgard1.flags_lo, MALI_WRITES_GLOBAL, ss->writes_global);
+ memcpy(&meta->midgard_props, &prop, sizeof(prop));
}
}
}
}
-static void
-panfrost_frag_meta_rasterizer_update(struct panfrost_context *ctx,
- struct mali_shader_meta *fragmeta)
-{
- struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
-
- bool msaa = rast->multisample;
-
- /* TODO: Sample size */
- SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa);
- SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa);
-
- struct panfrost_shader_state *fs;
- fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
-
- /* EXT_shader_framebuffer_fetch requires the shader to be run
- * per-sample when outputs are read. */
- bool per_sample = ctx->min_samples > 1 || fs->outputs_read;
- SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample);
-
- fragmeta->depth_units = rast->offset_units * 2.0f;
- fragmeta->depth_factor = rast->offset_scale;
-
- /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
-
- SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri);
- SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri);
-
- SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near);
- SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far);
-}
-
-static void
-panfrost_frag_meta_zsa_update(struct panfrost_context *ctx,
- struct mali_shader_meta *fragmeta)
-{
- const struct panfrost_zsa_state *so = ctx->depth_stencil;
-
- SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST,
- so->base.stencil[0].enabled);
-
- fragmeta->stencil_mask_front = so->stencil_mask_front;
- fragmeta->stencil_mask_back = so->stencil_mask_back;
-
- /* Bottom bits for stencil ref, exactly one word */
- fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0];
-
- /* If back-stencil is not enabled, use the front values */
-
- if (so->base.stencil[1].enabled)
- fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1];
- else
- fragmeta->stencil_back = fragmeta->stencil_front;
-
- SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK,
- so->base.depth.writemask);
-
- fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
- fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(
- so->base.depth.enabled ? so->base.depth.func : PIPE_FUNC_ALWAYS));
-}
-
static bool
panfrost_fs_required(
struct panfrost_shader_state *fs,
return (fs->writes_depth || fs->writes_stencil);
}
-static void
-panfrost_frag_meta_blend_update(struct panfrost_context *ctx,
- struct mali_shader_meta *fragmeta,
- struct panfrost_blend_final *blend)
-{
- struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
- const struct panfrost_device *dev = pan_device(ctx->base.screen);
- struct panfrost_shader_state *fs;
- fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
-
- SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER,
- (dev->quirks & MIDGARD_SFBD) && ctx->blend &&
- !ctx->blend->base.dither);
-
- SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE,
- ctx->blend->base.alpha_to_coverage);
-
- /* Get blending setup */
- unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs;
-
- /* Disable shader execution if we can */
- if (dev->quirks & MIDGARD_SHADERLESS
- && !panfrost_fs_required(fs, blend, rt_count)) {
- fragmeta->shader = 0;
- fragmeta->attribute_count = 0;
- fragmeta->varying_count = 0;
- fragmeta->texture_count = 0;
- fragmeta->sampler_count = 0;
-
- /* This feature is not known to work on Bifrost */
- fragmeta->midgard1.work_count = 1;
- fragmeta->midgard1.uniform_count = 0;
- fragmeta->midgard1.uniform_buffer_count = 0;
- }
-
- /* If there is a blend shader, work registers are shared. We impose 8
- * work registers as a limit for blend shaders. Should be lower XXX */
-
- if (!(dev->quirks & IS_BIFROST)) {
- for (unsigned c = 0; c < rt_count; ++c) {
- if (blend[c].is_shader) {
- fragmeta->midgard1.work_count =
- MAX2(fragmeta->midgard1.work_count, 8);
- }
- }
- }
-
- /* Even on MFBD, the shader descriptor gets blend shaders. It's *also*
- * copied to the blend_meta appended (by convention), but this is the
- * field actually read by the hardware. (Or maybe both are read...?).
- * Specify the last RTi with a blend shader. */
-
- fragmeta->blend.shader = 0;
-
- for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) {
- if (!blend[rt].is_shader)
- continue;
-
- fragmeta->blend.shader = blend[rt].shader.gpu |
- blend[rt].shader.first_tag;
- break;
- }
-
- if (dev->quirks & MIDGARD_SFBD) {
- /* When only a single render target platform is used, the blend
- * information is inside the shader meta itself. We additionally
- * need to signal CAN_DISCARD for nontrivial blend modes (so
- * we're able to read back the destination buffer) */
-
- SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER,
- blend[0].is_shader);
-
- if (!blend[0].is_shader) {
- fragmeta->blend.equation = blend[0].equation.equation;
- fragmeta->blend.constant = blend[0].equation.constant;
- }
-
- SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD,
- blend[0].load_dest);
-
- batch->draws |= PIPE_CLEAR_COLOR0;
- return;
- }
-
- if (dev->quirks & IS_BIFROST) {
- bool no_blend = true;
-
- for (unsigned i = 0; i < rt_count; ++i)
- no_blend &= (!blend[i].load_dest | blend[i].no_colour);
-
- SET_BIT(fragmeta->bifrost1.unk1, MALI_BIFROST_EARLY_Z,
- !fs->can_discard && !fs->writes_depth && no_blend);
- }
-}
-
static void
panfrost_emit_blend(struct panfrost_batch *batch, void *rts,
struct panfrost_blend_final *blend)
}
static void
-panfrost_frag_shader_meta_init(struct panfrost_context *ctx,
+panfrost_emit_frag_shader(struct panfrost_context *ctx,
struct mali_shader_meta *fragmeta,
struct panfrost_blend_final *blend)
{
fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
- bool msaa = ctx->rasterizer->base.multisample;
+ struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
+ const struct panfrost_zsa_state *zsa = ctx->depth_stencil;
+ unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs;
+
+ memset(fragmeta, 0, sizeof(*fragmeta));
+
+ fragmeta->shader = fs->shader;
+ fragmeta->attribute_count = fs->attribute_count;
+ fragmeta->varying_count = fs->varying_count;
+ fragmeta->texture_count = ctx->sampler_view_count[PIPE_SHADER_FRAGMENT];
+ fragmeta->sampler_count = ctx->sampler_count[PIPE_SHADER_FRAGMENT];
+
+ if (dev->quirks & IS_BIFROST) {
+ struct mali_bifrost_properties_packed prop;
+
+ bool no_blend = true;
+
+ for (unsigned i = 0; i < rt_count; ++i)
+ no_blend &= (!blend[i].load_dest | blend[i].no_colour);
+
+ pan_pack(&prop, BIFROST_PROPERTIES, cfg) {
+ cfg.unknown = 0x950020; /* XXX */
+ cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT);
+ cfg.early_z_enable = !fs->can_discard && !fs->writes_depth && no_blend;
+ }
+
+ memcpy(&fragmeta->bifrost_props, &prop, sizeof(prop));
+
+ fragmeta->bifrost2.preload_regs = 0x1;
+ SET_BIT(fragmeta->bifrost2.preload_regs, 0x10, fs->reads_frag_coord);
+
+ fragmeta->bifrost2.uniform_count = fs->uniform_count;
+ } else {
+ struct mali_midgard_properties_packed prop;
+
+ /* Reasons to disable early-Z from a shader perspective */
+ bool late_z = fs->can_discard || fs->writes_global ||
+ fs->writes_depth || fs->writes_stencil;
+
+ /* Reasons to disable early-Z from a CSO perspective */
+ bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
+
+ /* If either depth or stencil is enabled, discard matters */
+ bool zs_enabled =
+ (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) ||
+ zsa->base.stencil[0].enabled;
+
+ bool has_blend_shader = false;
+
+ for (unsigned c = 0; c < rt_count; ++c)
+ has_blend_shader |= blend[c].is_shader;
+
+ pan_pack(&prop, MIDGARD_PROPERTIES, cfg) {
+ cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT);
+ cfg.uniform_count = fs->uniform_count;
+ cfg.work_register_count = fs->work_reg_count;
+ cfg.writes_globals = fs->writes_global;
+ cfg.suppress_inf_nan = true; /* XXX */
+
+ /* TODO: Reduce this limit? */
+ if (has_blend_shader)
+ cfg.work_register_count = MAX2(cfg.work_register_count, 8);
+
+ cfg.stencil_from_shader = fs->writes_stencil;
+ cfg.helper_invocation_enable = fs->helper_invocations;
+ cfg.depth_source = fs->writes_depth ?
+ MALI_DEPTH_SOURCE_SHADER :
+ MALI_DEPTH_SOURCE_FIXED_FUNCTION;
+
+ /* Depend on other state */
+ cfg.early_z_enable = !(late_z || alpha_to_coverage);
+ cfg.reads_tilebuffer = fs->outputs_read || (!zs_enabled && fs->can_discard);
+ cfg.reads_depth_stencil = zs_enabled && fs->can_discard;
+ }
+
+ memcpy(&fragmeta->midgard_props, &prop, sizeof(prop));
+ }
+
+ bool msaa = rast->multisample;
fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0;
fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10;
fragmeta->unknown2_4 = 0x4e0;
- /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this
- * is required (independent of 32-bit/64-bit descriptors), or why it's
- * not used on later GPU revisions. Otherwise, all shader jobs fault on
- * these earlier chips (perhaps this is a chicken bit of some kind).
- * More investigation is needed. */
+ /* TODO: Sample size */
+ SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa);
+ SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa);
+
+ /* EXT_shader_framebuffer_fetch requires the shader to be run
+ * per-sample when outputs are read. */
+ bool per_sample = ctx->min_samples > 1 || fs->outputs_read;
+ SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample);
- SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD);
+ fragmeta->depth_units = rast->offset_units * 2.0f;
+ fragmeta->depth_factor = rast->offset_scale;
- if (dev->quirks & IS_BIFROST) {
- /* TODO */
- } else {
- /* Depending on whether it's legal to in the given shader, we try to
- * enable early-z testing. TODO: respect e-z force */
+ /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
+
+ SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri);
+ SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri);
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z,
- !fs->can_discard && !fs->writes_global &&
- !fs->writes_depth && !fs->writes_stencil &&
- !ctx->blend->base.alpha_to_coverage);
+ SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near);
+ SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far);
- /* Add the writes Z/S flags if needed. */
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth);
- SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil);
+ SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST,
+ zsa->base.stencil[0].enabled);
- /* Any time texturing is used, derivatives are implicitly calculated,
- * so we need to enable helper invocations */
+ fragmeta->stencil_mask_front = zsa->stencil_mask_front;
+ fragmeta->stencil_mask_back = zsa->stencil_mask_back;
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS,
- fs->helper_invocations);
+ /* Bottom bits for stencil ref, exactly one word */
+ fragmeta->stencil_front.opaque[0] = zsa->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0];
- /* If discard is enabled, which bit we set to convey this
- * depends on if depth/stencil is used for the draw or not.
- * Just one of depth OR stencil is enough to trigger this. */
+ /* If back-stencil is not enabled, use the front values */
- const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base;
- bool zs_enabled =
- fs->writes_depth || fs->writes_stencil ||
- (zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS) ||
- zsa->stencil[0].enabled;
+ if (zsa->base.stencil[1].enabled)
+ fragmeta->stencil_back.opaque[0] = zsa->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1];
+ else
+ fragmeta->stencil_back = fragmeta->stencil_front;
+
+ SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK,
+ zsa->base.depth.writemask);
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER,
- fs->outputs_read || (!zs_enabled && fs->can_discard));
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard);
+ fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
+ fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(
+ zsa->base.depth.enabled ? zsa->base.depth.func : PIPE_FUNC_ALWAYS));
+
+ SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE,
+ ctx->blend->base.alpha_to_coverage);
+
+ /* Disable shader execution if we can */
+ if (dev->quirks & MIDGARD_SHADERLESS
+ && !panfrost_fs_required(fs, blend, rt_count)) {
+ fragmeta->shader = 0x1;
+ fragmeta->attribute_count = 0;
+ fragmeta->varying_count = 0;
+ fragmeta->texture_count = 0;
+ fragmeta->sampler_count = 0;
+
+ /* This feature is not known to work on Bifrost */
+ struct mali_midgard_properties_packed prop;
+
+ pan_pack(&prop, MIDGARD_PROPERTIES, cfg) {
+ cfg.work_register_count = 1;
+ cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
+ cfg.early_z_enable = true;
+ }
+
+ memcpy(&fragmeta->midgard_props, &prop, sizeof(prop));
}
- panfrost_frag_meta_rasterizer_update(ctx, fragmeta);
- panfrost_frag_meta_zsa_update(ctx, fragmeta);
- panfrost_frag_meta_blend_update(ctx, fragmeta, blend);
+ if (dev->quirks & MIDGARD_SFBD) {
+ /* When only a single render target platform is used, the blend
+ * information is inside the shader meta itself. We additionally
+ * need to signal CAN_DISCARD for nontrivial blend modes (so
+ * we're able to read back the destination buffer) */
+
+ SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER,
+ blend[0].is_shader);
+
+ if (blend[0].is_shader) {
+ fragmeta->blend.shader = blend[0].shader.gpu |
+ blend[0].shader.first_tag;
+ } else {
+ fragmeta->blend.equation = blend[0].equation.equation;
+ fragmeta->blend.constant = blend[0].equation.constant;
+ }
+
+ SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD,
+ blend[0].load_dest);
+
+ fragmeta->unknown2_4 |= 0x10;
+ SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, !ctx->blend->base.dither);
+ } else if (!(dev->quirks & IS_BIFROST)) {
+ /* Bug where MRT-capable hw apparently reads the last blend
+ * shader from here instead of the usual location? */
+
+ for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) {
+ if (!blend[rt].is_shader)
+ continue;
+
+ fragmeta->blend.shader = blend[rt].shader.gpu |
+ blend[rt].shader.first_tag;
+ break;
+ }
+ }
}
void
struct mali_shader_meta meta;
- panfrost_shader_meta_init(ctx, st, &meta);
-
/* Add the shader BO to the batch. */
panfrost_batch_add_bo(batch, ss->bo,
PAN_BO_ACCESS_PRIVATE |
for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c)
blend[c] = panfrost_get_blend_for_context(ctx, c);
- panfrost_frag_shader_meta_init(ctx, &meta, blend);
+ panfrost_emit_frag_shader(ctx, &meta, blend);
if (!(dev->quirks & MIDGARD_SFBD))
panfrost_emit_blend(batch, rts, blend);
+ else
+ batch->draws |= PIPE_CLEAR_COLOR0;
xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, sizeof(meta));
shader_ptr = xfer.gpu;
} else {
+ panfrost_emit_compute_shader(ctx, st, &meta);
+
shader_ptr = panfrost_pool_upload(&batch->pool, &meta,
sizeof(meta));
}
/* Upload uniforms as a UBO */
- if (ss->uniform_count) {
+ if (size) {
pan_pack(ubo_ptr, UNIFORM_BUFFER, cfg) {
- cfg.entries = ss->uniform_count;
+ cfg.entries = DIV_ROUND_UP(size, 16);
cfg.pointer = transfer.gpu;
}
} else {
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