}
static void
-panfrost_compute_shader_meta_init(struct panfrost_context *ctx,
+panfrost_emit_compute_shader(struct panfrost_context *ctx,
enum pipe_shader_type st,
struct mali_shader_meta *meta)
{
meta->sampler_count = ctx->sampler_count[st];
if (dev->quirks & IS_BIFROST) {
- meta->bifrost1.unk1 = 0x800000;
+ struct mali_bifrost_properties_packed prop;
+
+ pan_pack(&prop, BIFROST_PROPERTIES, cfg) {
+ cfg.unknown = 0x800000; /* XXX */
+ cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st);
+ }
+
+ memcpy(&meta->bifrost_props, &prop, sizeof(prop));
+
meta->bifrost2.preload_regs = 0xC0;
meta->bifrost2.uniform_count = ss->uniform_count;
- meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
} else {
- meta->midgard1.uniform_count = ss->uniform_count;
- meta->midgard1.work_count = ss->work_reg_count;
-
- /* TODO: This is not conformant on ES3 */
- meta->midgard1.flags_hi = MALI_SUPPRESS_INF_NAN;
-
- meta->midgard1.flags_lo = 0x20;
- meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
+ struct mali_midgard_properties_packed prop;
+
+ pan_pack(&prop, MIDGARD_PROPERTIES, cfg) {
+ cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st);
+ cfg.uniform_count = ss->uniform_count;
+ cfg.work_register_count = ss->work_reg_count;
+ cfg.writes_globals = ss->writes_global;
+ cfg.suppress_inf_nan = true; /* XXX */
+ }
- SET_BIT(meta->midgard1.flags_lo, MALI_WRITES_GLOBAL, ss->writes_global);
+ memcpy(&meta->midgard_props, &prop, sizeof(prop));
}
}
}
static void
-panfrost_frag_shader_meta_init(struct panfrost_context *ctx,
+panfrost_emit_frag_shader(struct panfrost_context *ctx,
struct mali_shader_meta *fragmeta,
struct panfrost_blend_final *blend)
{
struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
const struct panfrost_zsa_state *zsa = ctx->depth_stencil;
+ unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs;
memset(fragmeta, 0, sizeof(*fragmeta));
fragmeta->sampler_count = ctx->sampler_count[PIPE_SHADER_FRAGMENT];
if (dev->quirks & IS_BIFROST) {
- /* First clause ATEST |= 0x4000000.
- * Lefs than 32 regs |= 0x200 */
- fragmeta->bifrost1.unk1 = 0x950020;
+ struct mali_bifrost_properties_packed prop;
+
+ bool no_blend = true;
+
+ for (unsigned i = 0; i < rt_count; ++i)
+ no_blend &= (!blend[i].load_dest | blend[i].no_colour);
+
+ pan_pack(&prop, BIFROST_PROPERTIES, cfg) {
+ cfg.unknown = 0x950020; /* XXX */
+ cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT);
+ cfg.early_z_enable = !fs->can_discard && !fs->writes_depth && no_blend;
+ }
+
+ memcpy(&fragmeta->bifrost_props, &prop, sizeof(prop));
- fragmeta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT);
fragmeta->bifrost2.preload_regs = 0x1;
SET_BIT(fragmeta->bifrost2.preload_regs, 0x10, fs->reads_frag_coord);
fragmeta->bifrost2.uniform_count = fs->uniform_count;
} else {
- fragmeta->midgard1.uniform_count = fs->uniform_count;
- fragmeta->midgard1.work_count = fs->work_reg_count;
-
- /* TODO: This is not conformant on ES3 */
- fragmeta->midgard1.flags_hi = MALI_SUPPRESS_INF_NAN;
+ struct mali_midgard_properties_packed prop;
- fragmeta->midgard1.flags_lo = 0x20;
- fragmeta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT);
-
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_GLOBAL, fs->writes_global);
- }
-
- bool msaa = rast->multisample;
- fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0;
+ /* Reasons to disable early-Z from a shader perspective */
+ bool late_z = fs->can_discard || fs->writes_global ||
+ fs->writes_depth || fs->writes_stencil;
- fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10;
- fragmeta->unknown2_4 = 0x4e0;
+ /* Reasons to disable early-Z from a CSO perspective */
+ bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
- /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this
- * is required (independent of 32-bit/64-bit descriptors), or why it's
- * not used on later GPU revisions. Otherwise, all shader jobs fault on
- * these earlier chips (perhaps this is a chicken bit of some kind).
- * More investigation is needed. */
+ /* If either depth or stencil is enabled, discard matters */
+ bool zs_enabled =
+ (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) ||
+ zsa->base.stencil[0].enabled;
- SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD);
+ bool has_blend_shader = false;
- if (dev->quirks & IS_BIFROST) {
- /* TODO */
- } else {
- /* Depending on whether it's legal to in the given shader, we try to
- * enable early-z testing. TODO: respect e-z force */
+ for (unsigned c = 0; c < rt_count; ++c)
+ has_blend_shader |= blend[c].is_shader;
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z,
- !fs->can_discard && !fs->writes_global &&
- !fs->writes_depth && !fs->writes_stencil &&
- !ctx->blend->base.alpha_to_coverage);
+ pan_pack(&prop, MIDGARD_PROPERTIES, cfg) {
+ cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT);
+ cfg.uniform_count = fs->uniform_count;
+ cfg.work_register_count = fs->work_reg_count;
+ cfg.writes_globals = fs->writes_global;
+ cfg.suppress_inf_nan = true; /* XXX */
- /* Add the writes Z/S flags if needed. */
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth);
- SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil);
+ /* TODO: Reduce this limit? */
+ if (has_blend_shader)
+ cfg.work_register_count = MAX2(cfg.work_register_count, 8);
- /* Any time texturing is used, derivatives are implicitly calculated,
- * so we need to enable helper invocations */
+ cfg.stencil_from_shader = fs->writes_stencil;
+ cfg.helper_invocation_enable = fs->helper_invocations;
+ cfg.depth_source = fs->writes_depth ?
+ MALI_DEPTH_SOURCE_SHADER :
+ MALI_DEPTH_SOURCE_FIXED_FUNCTION;
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS,
- fs->helper_invocations);
+ /* Depend on other state */
+ cfg.early_z_enable = !(late_z || alpha_to_coverage);
+ cfg.reads_tilebuffer = fs->outputs_read || (!zs_enabled && fs->can_discard);
+ cfg.reads_depth_stencil = zs_enabled && fs->can_discard;
+ }
- /* If discard is enabled, which bit we set to convey this
- * depends on if depth/stencil is used for the draw or not.
- * Just one of depth OR stencil is enough to trigger this. */
+ memcpy(&fragmeta->midgard_props, &prop, sizeof(prop));
+ }
- bool zs_enabled =
- fs->writes_depth || fs->writes_stencil ||
- (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) ||
- zsa->base.stencil[0].enabled;
+ bool msaa = rast->multisample;
+ fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0;
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER,
- fs->outputs_read || (!zs_enabled && fs->can_discard));
- SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard);
- }
+ fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10;
+ fragmeta->unknown2_4 = 0x4e0;
/* TODO: Sample size */
SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa);
fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(
zsa->base.depth.enabled ? zsa->base.depth.func : PIPE_FUNC_ALWAYS));
- SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER,
- (dev->quirks & MIDGARD_SFBD) && ctx->blend &&
- !ctx->blend->base.dither);
-
SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE,
ctx->blend->base.alpha_to_coverage);
- /* Get blending setup */
- unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs;
-
/* Disable shader execution if we can */
if (dev->quirks & MIDGARD_SHADERLESS
&& !panfrost_fs_required(fs, blend, rt_count)) {
- fragmeta->shader = 0;
+ fragmeta->shader = 0x1;
fragmeta->attribute_count = 0;
fragmeta->varying_count = 0;
fragmeta->texture_count = 0;
fragmeta->sampler_count = 0;
/* This feature is not known to work on Bifrost */
- fragmeta->midgard1.work_count = 1;
- fragmeta->midgard1.uniform_count = 0;
- fragmeta->midgard1.uniform_buffer_count = 0;
- }
-
- /* If there is a blend shader, work registers are shared. We impose 8
- * work registers as a limit for blend shaders. Should be lower XXX */
+ struct mali_midgard_properties_packed prop;
- if (!(dev->quirks & IS_BIFROST)) {
- for (unsigned c = 0; c < rt_count; ++c) {
- if (blend[c].is_shader) {
- fragmeta->midgard1.work_count =
- MAX2(fragmeta->midgard1.work_count, 8);
- }
+ pan_pack(&prop, MIDGARD_PROPERTIES, cfg) {
+ cfg.work_register_count = 1;
+ cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
+ cfg.early_z_enable = true;
}
- }
-
- /* Even on MFBD, the shader descriptor gets blend shaders. It's *also*
- * copied to the blend_meta appended (by convention), but this is the
- * field actually read by the hardware. (Or maybe both are read...?).
- * Specify the last RTi with a blend shader. */
-
- fragmeta->blend.shader = 0;
- for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) {
- if (!blend[rt].is_shader)
- continue;
-
- fragmeta->blend.shader = blend[rt].shader.gpu |
- blend[rt].shader.first_tag;
- break;
+ memcpy(&fragmeta->midgard_props, &prop, sizeof(prop));
}
if (dev->quirks & MIDGARD_SFBD) {
SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER,
blend[0].is_shader);
- if (!blend[0].is_shader) {
+ if (blend[0].is_shader) {
+ fragmeta->blend.shader = blend[0].shader.gpu |
+ blend[0].shader.first_tag;
+ } else {
fragmeta->blend.equation = blend[0].equation.equation;
fragmeta->blend.constant = blend[0].equation.constant;
}
SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD,
blend[0].load_dest);
- }
- if (dev->quirks & IS_BIFROST) {
- bool no_blend = true;
+ fragmeta->unknown2_4 |= 0x10;
+ SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, !ctx->blend->base.dither);
+ } else if (!(dev->quirks & IS_BIFROST)) {
+ /* Bug where MRT-capable hw apparently reads the last blend
+ * shader from here instead of the usual location? */
- for (unsigned i = 0; i < rt_count; ++i)
- no_blend &= (!blend[i].load_dest | blend[i].no_colour);
+ for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) {
+ if (!blend[rt].is_shader)
+ continue;
- SET_BIT(fragmeta->bifrost1.unk1, MALI_BIFROST_EARLY_Z,
- !fs->can_discard && !fs->writes_depth && no_blend);
+ fragmeta->blend.shader = blend[rt].shader.gpu |
+ blend[rt].shader.first_tag;
+ break;
+ }
}
}
for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c)
blend[c] = panfrost_get_blend_for_context(ctx, c);
- panfrost_frag_shader_meta_init(ctx, &meta, blend);
+ panfrost_emit_frag_shader(ctx, &meta, blend);
if (!(dev->quirks & MIDGARD_SFBD))
panfrost_emit_blend(batch, rts, blend);
shader_ptr = xfer.gpu;
} else {
- panfrost_compute_shader_meta_init(ctx, st, &meta);
+ panfrost_emit_compute_shader(ctx, st, &meta);
shader_ptr = panfrost_pool_upload(&batch->pool, &meta,
sizeof(meta));
projects / mesa.git / blobdiff