#include "pan_blend_shaders.h"
#include "pan_cmdstream.h"
#include "pan_util.h"
-#include "pandecode/decode.h"
+#include "decode.h"
#include "util/pan_lower_framebuffer.h"
struct midgard_tiler_descriptor
panfrost_batch_clear(batch, buffers, color, depth, stencil);
}
-/* Reset per-frame context, called on context initialisation as well as after
- * flushing a frame */
-
-void
-panfrost_invalidate_frame(struct panfrost_context *ctx)
-{
- /* TODO: When does this need to be handled? */
- ctx->active_queries = true;
-}
-
bool
panfrost_writes_point_size(struct panfrost_context *ctx)
{
return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS;
}
-void
-panfrost_vertex_state_upd_attr_offs(struct panfrost_context *ctx,
- struct mali_vertex_tiler_postfix *vertex_postfix)
-{
- if (!ctx->vertex)
- return;
-
- struct panfrost_vertex_state *so = ctx->vertex;
-
- /* Fixup offsets for the second pass. Recall that the hardware
- * calculates attribute addresses as:
- *
- * addr = base + (stride * vtx) + src_offset;
- *
- * However, on Mali, base must be aligned to 64-bytes, so we
- * instead let:
- *
- * base' = base & ~63 = base - (base & 63)
- *
- * To compensate when using base' (see emit_vertex_data), we have
- * to adjust src_offset by the masked off piece:
- *
- * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
- * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
- * = base + (stride * vtx) + src_offset
- * = addr;
- *
- * QED.
- */
-
- unsigned start = vertex_postfix->offset_start;
-
- for (unsigned i = 0; i < so->num_elements; ++i) {
- unsigned vbi = so->pipe[i].vertex_buffer_index;
- struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
-
- /* Adjust by the masked off bits of the offset. Make sure we
- * read src_offset from so->hw (which is not GPU visible)
- * rather than target (which is) due to caching effects */
-
- unsigned src_offset = so->pipe[i].src_offset;
-
- /* BOs aligned to 4k so guaranteed aligned to 64 */
- src_offset += (buf->buffer_offset & 63);
-
- /* Also, somewhat obscurely per-instance data needs to be
- * offset in response to a delayed start in an indexed draw */
-
- if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start)
- src_offset -= buf->stride * start;
-
- so->hw[i].src_offset = src_offset;
- }
-}
-
/* Compute number of UBOs active (more specifically, compute the highest UBO
* number addressable -- if there are gaps, include them in the count anyway).
* We always include UBO #0 in the count, since we *need* uniforms enabled for
panfrost_flush_all_batches(ctx, 0);
}
-#define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
+#define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
static int
g2m_draw_mode(enum pipe_prim_type mode)
/* Check if we're scissoring at all */
- if (!(ctx->rasterizer && ctx->rasterizer->base.scissor))
+ if (!ctx->rasterizer->base.scissor)
return false;
return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
assert(ctx->rasterizer != NULL);
if (!(ctx->draw_modes & (1 << mode))) {
- if (mode == PIPE_PRIM_QUADS && info->count == 4 && !ctx->rasterizer->base.flatshade) {
- mode = PIPE_PRIM_TRIANGLE_FAN;
- } else {
- if (info->count < 4) {
- /* Degenerate case? */
- return;
- }
-
- util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
- util_primconvert_draw_vbo(ctx->primconvert, info);
+ if (info->count < 4) {
+ /* Degenerate case? */
return;
}
+
+ util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
+ util_primconvert_draw_vbo(ctx->primconvert, info);
+ return;
}
/* Now that we have a guaranteed terminating path, find the job.
&primitive_size);
panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
- panfrost_emit_vertex_attr_meta(batch, &vertex_postfix);
panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
for (int i = 0; i < num_elements; ++i) {
- so->hw[i].index = i;
-
enum pipe_format fmt = elements[i].src_format;
const struct util_format_description *desc = util_format_description(fmt);
- so->hw[i].unknown1 = 0x2;
-
+ unsigned swizzle = 0;
if (dev->quirks & HAS_SWIZZLES)
- so->hw[i].swizzle = panfrost_translate_swizzle_4(desc->swizzle);
+ swizzle = panfrost_translate_swizzle_4(desc->swizzle);
else
- so->hw[i].swizzle = panfrost_bifrost_swizzle(desc->nr_channels);
+ swizzle = panfrost_bifrost_swizzle(desc->nr_channels);
enum mali_format hw_format = panfrost_pipe_format_table[desc->format].hw;
- so->hw[i].format = hw_format;
+ so->formats[i] = (hw_format << 12) | swizzle;
assert(hw_format);
}
/* Let's also prepare vertex builtins */
- so->hw[PAN_VERTEX_ID].format = MALI_R32UI;
if (dev->quirks & HAS_SWIZZLES)
- so->hw[PAN_VERTEX_ID].swizzle = panfrost_get_default_swizzle(1);
+ so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
else
- so->hw[PAN_VERTEX_ID].swizzle = panfrost_bifrost_swizzle(1);
+ so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
- so->hw[PAN_INSTANCE_ID].format = MALI_R32UI;
if (dev->quirks & HAS_SWIZZLES)
- so->hw[PAN_INSTANCE_ID].swizzle = panfrost_get_default_swizzle(1);
+ so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
else
- so->hw[PAN_INSTANCE_ID].swizzle = panfrost_bifrost_swizzle(1);
+ so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
return so;
}
so->base = *cso;
if (device->quirks & IS_BIFROST)
- panfrost_sampler_desc_init_bifrost(cso, &so->bifrost_hw);
+ panfrost_sampler_desc_init_bifrost(cso, (struct mali_bifrost_sampler_packed *) &so->hw);
else
- panfrost_sampler_desc_init(cso, &so->midgard_hw);
+ panfrost_sampler_desc_init(cso, &so->hw);
return so;
}
{
struct panfrost_device *dev = pan_device(ctx->base.screen);
struct pipe_rasterizer_state *rasterizer = &ctx->rasterizer->base;
- struct pipe_alpha_state *alpha = &ctx->depth_stencil->alpha;
bool is_fragment = (type == PIPE_SHADER_FRAGMENT);
- if (is_fragment && (alpha->enabled || variant->alpha_state.enabled)) {
- /* Make sure enable state is at least the same */
- if (alpha->enabled != variant->alpha_state.enabled) {
- return false;
- }
-
- /* Check that the contents of the test are the same */
- bool same_func = alpha->func == variant->alpha_state.func;
- bool same_ref = alpha->ref_value == variant->alpha_state.ref_value;
-
- if (!(same_func && same_ref)) {
- return false;
- }
- }
-
if (variant->outputs_read) {
struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
&variants->variants[variant];
if (type == PIPE_SHADER_FRAGMENT) {
- v->alpha_state = ctx->depth_stencil->alpha;
-
struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
}
so->texture_bo = prsrc->bo->gpu;
- so->layout = prsrc->layout;
+ so->modifier = prsrc->modifier;
unsigned char user_swizzle[4] = {
so->base.swizzle_r,
assert(texture->nr_samples <= 1);
}
- enum mali_texture_type type =
- panfrost_translate_texture_type(so->base.target);
+ enum mali_texture_dimension type =
+ panfrost_translate_texture_dimension(so->base.target);
if (device->quirks & IS_BIFROST) {
unsigned char composed_swizzle[4];
so->base.u.tex.first_layer,
so->base.u.tex.last_layer,
texture->nr_samples,
- type, prsrc->layout);
+ type, prsrc->modifier);
so->bo = panfrost_bo_create(device, size, 0);
- so->bifrost_descriptor = rzalloc(pctx, struct bifrost_texture_descriptor);
panfrost_new_texture_bifrost(
- so->bifrost_descriptor,
+ &so->bifrost_descriptor,
texture->width0, texture->height0,
depth, array_size,
format,
- type, prsrc->layout,
+ type, prsrc->modifier,
so->base.u.tex.first_level,
so->base.u.tex.last_level,
so->base.u.tex.first_layer,
so->base.u.tex.first_layer,
so->base.u.tex.last_layer,
texture->nr_samples,
- type, prsrc->layout);
- size += sizeof(struct mali_texture_descriptor);
+ type, prsrc->modifier);
+ size += MALI_MIDGARD_TEXTURE_LENGTH;
so->bo = panfrost_bo_create(device, size, 0);
texture->width0, texture->height0,
depth, array_size,
format,
- type, prsrc->layout,
+ type, prsrc->modifier,
so->base.u.tex.first_level,
so->base.u.tex.last_level,
so->base.u.tex.first_layer,
pipe_resource_reference(&pview->texture, NULL);
panfrost_bo_unreference(view->bo);
- if (view->bifrost_descriptor)
- ralloc_free(view->bifrost_descriptor);
ralloc_free(view);
}
buffers, start, count);
}
-/* Hints that a framebuffer should use AFBC where possible */
-
-static void
-panfrost_hint_afbc(
- struct panfrost_device *device,
- const struct pipe_framebuffer_state *fb)
-{
- /* AFBC implemenation incomplete; hide it */
- if (!(device->debug & PAN_DBG_AFBC)) return;
-
- /* Hint AFBC to the resources bound to each color buffer */
-
- for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
- struct pipe_surface *surf = fb->cbufs[i];
- struct panfrost_resource *rsrc = pan_resource(surf->texture);
- panfrost_resource_hint_layout(device, rsrc, MALI_TEXTURE_AFBC, 1);
- }
-
- /* Also hint it to the depth buffer */
-
- if (fb->zsbuf) {
- struct panfrost_resource *rsrc = pan_resource(fb->zsbuf->texture);
- panfrost_resource_hint_layout(device, rsrc, MALI_TEXTURE_AFBC, 1);
- }
-}
-
static void
panfrost_set_framebuffer_state(struct pipe_context *pctx,
const struct pipe_framebuffer_state *fb)
{
struct panfrost_context *ctx = pan_context(pctx);
- panfrost_hint_afbc(pan_device(pctx->screen), fb);
util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb);
ctx->batch = NULL;
- panfrost_invalidate_frame(ctx);
/* We may need to generate a new variant if the fragment shader is
* keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
ctx->base.bind_fs_state(&ctx->base, fs);
}
+static inline unsigned
+pan_pipe_to_stencil_op(enum pipe_stencil_op in)
+{
+ switch (in) {
+ case PIPE_STENCIL_OP_KEEP: return MALI_STENCIL_OP_KEEP;
+ case PIPE_STENCIL_OP_ZERO: return MALI_STENCIL_OP_ZERO;
+ case PIPE_STENCIL_OP_REPLACE: return MALI_STENCIL_OP_REPLACE;
+ case PIPE_STENCIL_OP_INCR: return MALI_STENCIL_OP_INCR_SAT;
+ case PIPE_STENCIL_OP_DECR: return MALI_STENCIL_OP_DECR_SAT;
+ case PIPE_STENCIL_OP_INCR_WRAP: return MALI_STENCIL_OP_INCR_WRAP;
+ case PIPE_STENCIL_OP_DECR_WRAP: return MALI_STENCIL_OP_DECR_WRAP;
+ case PIPE_STENCIL_OP_INVERT: return MALI_STENCIL_OP_INVERT;
+ default: unreachable("Invalid stencil op");
+ }
+}
+
+static inline void
+pan_pipe_to_stencil(const struct pipe_stencil_state *in, void *out)
+{
+ pan_pack(out, STENCIL, cfg) {
+ cfg.mask = in->valuemask;
+ cfg.compare_function = panfrost_translate_compare_func(in->func);
+ cfg.stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
+ cfg.depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
+ cfg.depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
+ }
+}
+
static void *
panfrost_create_depth_stencil_state(struct pipe_context *pipe,
- const struct pipe_depth_stencil_alpha_state *depth_stencil)
+ const struct pipe_depth_stencil_alpha_state *zsa)
{
- return mem_dup(depth_stencil, sizeof(*depth_stencil));
+ struct panfrost_zsa_state *so = CALLOC_STRUCT(panfrost_zsa_state);
+ so->base = *zsa;
+
+ pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
+ pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
+
+ so->stencil_mask_front = zsa->stencil[0].writemask;
+
+ if (zsa->stencil[1].enabled)
+ so->stencil_mask_back = zsa->stencil[1].writemask;
+ else
+ so->stencil_mask_back = so->stencil_mask_front;
+
+ /* Alpha lowered by frontend */
+ assert(!zsa->alpha.enabled);
+
+ /* TODO: Bounds test should be easy */
+ assert(!zsa->depth.bounds_test);
+
+ return so;
}
static void
void *cso)
{
struct panfrost_context *ctx = pan_context(pipe);
- struct pipe_depth_stencil_alpha_state *depth_stencil = cso;
- ctx->depth_stencil = depth_stencil;
-
- if (!depth_stencil)
- return;
-
- /* Alpha does not exist in the hardware (it's not in ES3), so it's
- * emulated in the fragment shader */
-
- if (depth_stencil->alpha.enabled) {
- /* We need to trigger a new shader (maybe) */
- ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
- }
-
- /* Bounds test not implemented */
- assert(!depth_stencil->depth.bounds_test);
+ struct panfrost_zsa_state *zsa = cso;
+ ctx->depth_stencil = zsa;
}
static void
/* Prepare for render! */
panfrost_batch_init(ctx);
- panfrost_invalidate_frame(ctx);
if (!(dev->quirks & IS_BIFROST)) {
for (unsigned c = 0; c < PIPE_MAX_COLOR_BUFS; ++c)
/* By default mask everything on */
ctx->sample_mask = ~0;
+ ctx->active_queries = true;
return gallium;
}
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