panfrost: Avoid postfix dep for vertex_data

[mesa.git] / src / gallium / drivers / panfrost / pan_context.c

diff --git a/src/gallium/drivers/panfrost/pan_context.c b/src/gallium/drivers/panfrost/pan_context.c
index e9ddba222565337c16303b4177038dc55fc8281b..9f22c2b698c24187f44f5ceeb0b9367f3ac2a824 100644 (file)
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -76,20 +76,14 @@ panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
         t.polygon_list_size = panfrost_tiler_full_size(
                                      width, height, t.hierarchy_mask, hierarchy);
 
-        /* Sanity check */
-
         if (vertex_count) {
-                struct panfrost_bo *tiler_heap;
-
-                tiler_heap = panfrost_batch_get_tiler_heap(batch);
                 t.polygon_list = panfrost_batch_get_polygon_list(batch,
                                                                  header_size +
                                                                  t.polygon_list_size);
 
 
-                /* Allow the entire tiler heap */
-                t.heap_start = tiler_heap->gpu;
-                t.heap_end = tiler_heap->gpu + tiler_heap->size;
+                t.heap_start = device->tiler_heap->gpu;
+                t.heap_end = device->tiler_heap->gpu + device->tiler_heap->size;
         } else {
                 struct panfrost_bo *tiler_dummy;
 
@@ -151,18 +145,6 @@ panfrost_writes_point_size(struct panfrost_context *ctx)
         return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS;
 }
 
-/* Compute number of UBOs active (more specifically, compute the highest UBO
- * number addressable -- if there are gaps, include them in the count anyway).
- * We always include UBO #0 in the count, since we *need* uniforms enabled for
- * sysvals. */
-
-unsigned
-panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
-{
-        unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
-        return 32 - __builtin_clz(mask);
-}
-
 /* The entire frame is in memory -- send it off to the kernel! */
 
 void
@@ -337,21 +319,27 @@ panfrost_draw_vbo(
                                         1, 1, 1);
 
         /* Emit all sort of descriptors. */
-        panfrost_emit_vertex_data(batch, &vertex_postfix);
+        mali_ptr push_vert = 0, push_frag = 0, attribs = 0;
+
+        vertex_postfix.attribute_meta = panfrost_emit_vertex_data(batch, &attribs);
+        vertex_postfix.attributes = attribs;
         panfrost_emit_varying_descriptor(batch,
                                          ctx->padded_count *
                                          ctx->instance_count,
                                          &vertex_postfix, &tiler_postfix,
                                          &primitive_size);
-        panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
-        panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
-        panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
-        panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
-        panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
-        panfrost_emit_texture_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
-        panfrost_emit_const_buf(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
-        panfrost_emit_const_buf(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
-        panfrost_emit_viewport(batch, &tiler_postfix);
+        vertex_postfix.sampler_descriptor = panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX);
+        tiler_postfix.sampler_descriptor = panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT);
+        vertex_postfix.textures = panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX);
+        tiler_postfix.textures = panfrost_emit_texture_descriptors(batch, PIPE_SHADER_FRAGMENT);
+        vertex_postfix.uniform_buffers = panfrost_emit_const_buf(batch, PIPE_SHADER_VERTEX, &push_vert);
+        tiler_postfix.uniform_buffers = panfrost_emit_const_buf(batch, PIPE_SHADER_FRAGMENT, &push_frag);
+        vertex_postfix.uniforms = push_vert;
+        tiler_postfix.uniforms = push_frag;
+        tiler_postfix.viewport = panfrost_emit_viewport(batch);
+
+        vertex_postfix.shader = panfrost_emit_compute_shader_meta(batch, PIPE_SHADER_VERTEX);
+        tiler_postfix.shader = panfrost_emit_frag_shader_meta(batch);
 
         panfrost_vt_update_primitive_size(ctx, &tiler_prefix, &primitive_size);
 
@@ -478,7 +466,7 @@ panfrost_create_shader_state(
         if (unlikely((dev->debug & PAN_DBG_PRECOMPILE) && cso->type == PIPE_SHADER_IR_NIR)) {
                 struct panfrost_context *ctx = pan_context(pctx);
 
-                struct panfrost_shader_state state;
+                struct panfrost_shader_state state = { 0 };
                 uint64_t outputs_written;
 
                 panfrost_shader_compile(ctx, PIPE_SHADER_IR_NIR,
@@ -504,10 +492,15 @@ panfrost_delete_shader_state(
         for (unsigned i = 0; i < cso->variant_count; ++i) {
                 struct panfrost_shader_state *shader_state = &cso->variants[i];
                 panfrost_bo_unreference(shader_state->bo);
+
+                if (shader_state->upload.rsrc)
+                        pipe_resource_reference(&shader_state->upload.rsrc, NULL);
+
                 shader_state->bo = NULL;
         }
         free(cso->variants);
 
+
         free(so);
 }
 
@@ -1064,14 +1057,15 @@ panfrost_create_depth_stencil_state(struct pipe_context *pipe,
         so->base = *zsa;
 
         pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
-        pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
-
         so->stencil_mask_front = zsa->stencil[0].writemask;
 
-        if (zsa->stencil[1].enabled)
+        if (zsa->stencil[1].enabled) {
+                pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
                 so->stencil_mask_back = zsa->stencil[1].writemask;
-        else
+        } else {
+                so->stencil_back = so->stencil_front;
                 so->stencil_mask_back = so->stencil_mask_front;
+        }
 
         /* Alpha lowered by frontend */
         assert(!zsa->alpha.enabled);
@@ -1177,6 +1171,7 @@ panfrost_destroy(struct pipe_context *pipe)
 
         util_unreference_framebuffer_state(&panfrost->pipe_framebuffer);
         u_upload_destroy(pipe->stream_uploader);
+        u_upload_destroy(panfrost->state_uploader);
 
         ralloc_free(pipe);
 }
@@ -1445,7 +1440,9 @@ panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
 
         gallium->stream_uploader = u_upload_create_default(gallium);
         gallium->const_uploader = gallium->stream_uploader;
-        assert(gallium->stream_uploader);
+
+        ctx->state_uploader = u_upload_create(gallium, 4096,
+                        PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_DYNAMIC, 0);
 
         /* All of our GPUs support ES mode. Midgard supports additionally
          * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */