- return vs->writes_point_size && ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.draw_mode == MALI_POINTS;
-}
-
-/* Stage the attribute descriptors so we can adjust src_offset
- * to let BOs align nicely */
-
-static void
-panfrost_stage_attributes(struct panfrost_context *ctx)
-{
- struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
- struct panfrost_vertex_state *so = ctx->vertex;
-
- size_t sz = sizeof(struct mali_attr_meta) * PAN_MAX_ATTRIBUTE;
- struct panfrost_transfer transfer = panfrost_allocate_transient(batch, sz);
- struct mali_attr_meta *target = (struct mali_attr_meta *) transfer.cpu;
-
- /* Copy as-is for the first pass */
- memcpy(target, so->hw, sz);
-
- /* Fixup offsets for the second pass. Recall that the hardware
- * calculates attribute addresses as:
- *
- * addr = base + (stride * vtx) + src_offset;
- *
- * However, on Mali, base must be aligned to 64-bytes, so we
- * instead let:
- *
- * base' = base & ~63 = base - (base & 63)
- *
- * To compensate when using base' (see emit_vertex_data), we have
- * to adjust src_offset by the masked off piece:
- *
- * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
- * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
- * = base + (stride * vtx) + src_offset
- * = addr;
- *
- * QED.
- */
-
- unsigned start = ctx->payloads[PIPE_SHADER_VERTEX].offset_start;
-
- for (unsigned i = 0; i < so->num_elements; ++i) {
- unsigned vbi = so->pipe[i].vertex_buffer_index;
- struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
-
- /* Adjust by the masked off bits of the offset. Make sure we
- * read src_offset from so->hw (which is not GPU visible)
- * rather than target (which is) due to caching effects */
-
- unsigned src_offset = so->pipe[i].src_offset;
-
- /* BOs aligned to 4k so guaranteed aligned to 64 */
- src_offset += (buf->buffer_offset & 63);
-
- /* Also, somewhat obscurely per-instance data needs to be
- * offset in response to a delayed start in an indexed draw */
-
- if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start)
- src_offset -= buf->stride * start;
-
- target[i].src_offset = src_offset;
- }
-
- /* Let's also include vertex builtins */
-
- struct mali_attr_meta builtin = {
- .format = MALI_R32UI,
- .swizzle = panfrost_get_default_swizzle(1)
- };
-
- /* See mali_attr_meta specification for the magic number */
-
- builtin.index = so->vertexid_index;
- memcpy(&target[PAN_VERTEX_ID], &builtin, 4);
-
- builtin.index = so->vertexid_index + 1;
- memcpy(&target[PAN_INSTANCE_ID], &builtin, 4);
-
- ctx->payloads[PIPE_SHADER_VERTEX].postfix.attribute_meta = transfer.gpu;
-}
-
-/* Compute number of UBOs active (more specifically, compute the highest UBO
- * number addressable -- if there are gaps, include them in the count anyway).
- * We always include UBO #0 in the count, since we *need* uniforms enabled for
- * sysvals. */
-
-unsigned
-panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
-{
- unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
- return 32 - __builtin_clz(mask);
-}
-
-/* Go through dirty flags and actualise them in the cmdstream. */
-
-static void
-panfrost_emit_for_draw(struct panfrost_context *ctx)
-{
- struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
-
- panfrost_batch_add_fbo_bos(batch);
-
- for (int i = 0; i <= PIPE_SHADER_FRAGMENT; ++i)
- panfrost_vt_attach_framebuffer(ctx, &ctx->payloads[i]);
-
- panfrost_emit_vertex_data(batch);
-
- /* Varyings emitted for -all- geometry */
- unsigned total_count = ctx->padded_count * ctx->instance_count;
- panfrost_emit_varying_descriptor(ctx, total_count);
-
- panfrost_batch_set_requirements(batch);
-
- panfrost_vt_update_rasterizer(ctx, &ctx->payloads[PIPE_SHADER_FRAGMENT]);
- panfrost_vt_update_occlusion_query(ctx, &ctx->payloads[PIPE_SHADER_FRAGMENT]);
-
- panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX,
- &ctx->payloads[PIPE_SHADER_VERTEX]);
- panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT,
- &ctx->payloads[PIPE_SHADER_FRAGMENT]);
-
- /* We stage to transient, so always dirty.. */
- if (ctx->vertex)
- panfrost_stage_attributes(ctx);
-
- for (int i = 0; i <= PIPE_SHADER_FRAGMENT; ++i) {
- panfrost_emit_sampler_descriptors(batch, i, &ctx->payloads[i]);
- panfrost_emit_texture_descriptors(batch, i, &ctx->payloads[i]);
- panfrost_emit_const_buf(batch, i, &ctx->payloads[i]);
- }
-
- /* TODO: Upload the viewport somewhere more appropriate */
-
- panfrost_emit_viewport(batch, &ctx->payloads[PIPE_SHADER_FRAGMENT]);
-}
-
-/* Corresponds to exactly one draw, but does not submit anything */
-
-static void
-panfrost_queue_draw(struct panfrost_context *ctx)
-{
- /* Handle dirty flags now */
- panfrost_emit_for_draw(ctx);
-
- struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
-
- panfrost_emit_vertex_tiler_jobs(batch,
- &ctx->payloads[PIPE_SHADER_VERTEX],
- &ctx->payloads[PIPE_SHADER_FRAGMENT]);
- panfrost_batch_adjust_stack_size(batch);