Merge branch 'mesa_7_7_branch'

[mesa.git] / src / gallium / drivers / r300 / r300_reg.h

diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h
index d8d08fbe26417ff889ceab23295542b57a05cc88..0aa1da07f8bab41a2012b5f98942bd27279ec33c 100644 (file)
--- a/src/gallium/drivers/r300/r300_reg.h
+++ b/src/gallium/drivers/r300/r300_reg.h
@@ -2638,7 +2638,7 @@ enum {
        VE_COND_MUX_GTE                 = 25,
        VE_SET_GREATER_THAN             = 26,
        VE_SET_EQUAL                    = 27,
-       VE_SET_NOT_EQUAL                = 28,
+       VE_SET_NOT_EQUAL                = 28
 };
 
 enum {
@@ -2672,20 +2672,20 @@ enum {
        ME_PRED_SET_CLR                 = 25,
        ME_PRED_SET_INV                 = 26,
        ME_PRED_SET_POP                 = 27,
-       ME_PRED_SET_RESTORE             = 28,
+       ME_PRED_SET_RESTORE             = 28
 };
 
 enum {
        /* R3XX */
        PVS_MACRO_OP_2CLK_MADD          = 0,
-       PVS_MACRO_OP_2CLK_M2X_ADD       = 1,
+       PVS_MACRO_OP_2CLK_M2X_ADD       = 1
 };
 
 enum {
        PVS_SRC_REG_TEMPORARY           = 0,    /* Intermediate Storage */
        PVS_SRC_REG_INPUT               = 1,    /* Input Vertex Storage */
        PVS_SRC_REG_CONSTANT            = 2,    /* Constant State Storage */
-       PVS_SRC_REG_ALT_TEMPORARY       = 3,    /* Alternate Intermediate Storage */
+       PVS_SRC_REG_ALT_TEMPORARY       = 3     /* Alternate Intermediate Storage */
 };
 
 enum {
@@ -2694,7 +2694,7 @@ enum {
        PVS_DST_REG_OUT                 = 2,    /* Output Memory. Used for all outputs */
        PVS_DST_REG_OUT_REPL_X          = 3,    /* Output Memory & Replicate X to all channels */
        PVS_DST_REG_ALT_TEMPORARY       = 4,    /* Alternate Intermediate Storage */
-       PVS_DST_REG_INPUT               = 5,    /* Output Memory & Replicate X to all channels */
+       PVS_DST_REG_INPUT               = 5     /* Output Memory & Replicate X to all channels */
 };
 
 enum {
@@ -2703,7 +2703,7 @@ enum {
        PVS_SRC_SELECT_Z                = 2,    /* Select Z Component */
        PVS_SRC_SELECT_W                = 3,    /* Select W Component */
        PVS_SRC_SELECT_FORCE_0          = 4,    /* Force Component to 0.0 */
-       PVS_SRC_SELECT_FORCE_1          = 5,    /* Force Component to 1.0 */
+       PVS_SRC_SELECT_FORCE_1          = 5     /* Force Component to 1.0 */
 };
 
 /* PVS Opcode & Destination Operand Description */
@@ -2742,7 +2742,7 @@ enum {
        PVS_DST_ADDR_SEL_MASK           = 0x3,
        PVS_DST_ADDR_SEL_SHIFT          = 29,
        PVS_DST_ADDR_MODE_0_MASK        = 0x1,
-       PVS_DST_ADDR_MODE_0_SHIFT       = 31,
+       PVS_DST_ADDR_MODE_0_SHIFT       = 31
 };
 
 /* PVS Source Operand Description */
@@ -2777,7 +2777,7 @@ enum {
        PVS_SRC_ADDR_SEL_MASK           = 0x3,
        PVS_SRC_ADDR_SEL_SHIFT          = 29,
        PVS_SRC_ADDR_MODE_1_MASK        = 0x0,
-       PVS_SRC_ADDR_MODE_1_SHIFT       = 32,
+       PVS_SRC_ADDR_MODE_1_SHIFT       = 32
 };
 
 /*\}*/