#include "tgsi/tgsi_parse.h"
#include "pipe/p_config.h"
-#include "pipe/internal/p_winsys_screen.h"
#include "r300_context.h"
#include "r300_reg.h"
dstA == PIPE_BLENDFACTOR_ONE);
}
+static unsigned bgra_cmask(unsigned mask)
+{
+ /* Gallium uses RGBA color ordering while R300 expects BGRA. */
+
+ return ((mask & PIPE_MASK_R) << 2) |
+ ((mask & PIPE_MASK_B) >> 2) |
+ (mask & (PIPE_MASK_G | PIPE_MASK_A));
+}
+
/* Create a new blend state based on the CSO blend state.
*
* This encompasses alpha blending, logic/raster ops, and blend dithering. */
static void* r300_create_blend_state(struct pipe_context* pipe,
const struct pipe_blend_state* state)
{
+ struct r300_screen* r300screen = r300_screen(pipe->screen);
struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
- if (state->blend_enable)
+ if (state->rt[0].blend_enable)
{
- unsigned eqRGB = state->rgb_func;
- unsigned srcRGB = state->rgb_src_factor;
- unsigned dstRGB = state->rgb_dst_factor;
+ unsigned eqRGB = state->rt[0].rgb_func;
+ unsigned srcRGB = state->rt[0].rgb_src_factor;
+ unsigned dstRGB = state->rt[0].rgb_dst_factor;
- unsigned eqA = state->alpha_func;
- unsigned srcA = state->alpha_src_factor;
- unsigned dstA = state->alpha_dst_factor;
+ unsigned eqA = state->rt[0].alpha_func;
+ unsigned srcA = state->rt[0].alpha_src_factor;
+ unsigned dstA = state->rt[0].alpha_dst_factor;
/* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
* this is just the crappy D3D naming */
(state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
}
- /* Color Channel Mask */
- if (state->colormask & PIPE_MASK_R) {
- blend->color_channel_mask |= RB3D_COLOR_CHANNEL_MASK_RED_MASK0;
- }
- if (state->colormask & PIPE_MASK_G) {
- blend->color_channel_mask |= RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0;
- }
- if (state->colormask & PIPE_MASK_B) {
- blend->color_channel_mask |= RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0;
- }
- if (state->colormask & PIPE_MASK_A) {
- blend->color_channel_mask |= RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0;
+ /* Color channel masks for all MRTs. */
+ blend->color_channel_mask = bgra_cmask(state->rt[0].colormask);
+ if (r300screen->caps->is_r500 && state->independent_blend_enable) {
+ if (state->rt[1].blend_enable) {
+ blend->color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
+ }
+ if (state->rt[2].blend_enable) {
+ blend->color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
+ }
+ if (state->rt[3].blend_enable) {
+ blend->color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
+ }
}
if (state->dither) {
const struct pipe_blend_color* color)
{
struct r300_context* r300 = r300_context(pipe);
+ struct r300_screen* r300screen = r300_screen(pipe->screen);
struct r300_blend_color_state* state =
(struct r300_blend_color_state*)r300->blend_color_state.state;
union util_color uc;
float_to_fixed10(color->color[2]) |
(float_to_fixed10(color->color[1]) << 16);
+ r300->blend_color_state.size = r300screen->caps->is_r500 ? 3 : 2;
r300->blend_color_state.dirty = TRUE;
}
if (r300_screen(pipe->screen)->caps->has_tcl) {
memcpy(r300->clip_state.state, state, sizeof(struct pipe_clip_state));
- r300->clip_state.dirty = TRUE;
+ r300->clip_state.size = 29;
} else {
draw_flush(r300->draw);
draw_set_clip_state(r300->draw, state);
+ r300->clip_state.size = 2;
}
+
+ r300->clip_state.dirty = TRUE;
}
/* Create a new depth, stencil, and alpha state based on the CSO dsa state.
(r300_translate_stencil_op(state->stencil[1].zfail_op) <<
R300_S_BACK_ZFAIL_OP_SHIFT);
- /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
if (caps->is_r500)
{
dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
r300_translate_alpha_function(state->alpha.func) |
R300_FG_ALPHA_FUNC_ENABLE;
- /* XXX figure out why emitting 10bit alpha ref causes CS to dump */
- /* always use 8bit alpha ref */
+ /* We could use 10bit alpha ref but who needs that? */
dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
if (caps->is_r500)
void* state)
{
struct r300_context* r300 = r300_context(pipe);
+ struct r300_screen* r300screen = r300_screen(pipe->screen);
r300->dsa_state.state = state;
+ r300->dsa_state.size = r300screen->caps->is_r500 ? 8 : 6;
r300->dsa_state.dirty = TRUE;
}
FREE(state);
}
-static void r300_set_scissor_regs(const struct pipe_scissor_state* state,
- struct r300_scissor_regs *scissor,
- boolean is_r500)
-{
- if (is_r500) {
- scissor->top_left =
- (state->minx << R300_SCISSORS_X_SHIFT) |
- (state->miny << R300_SCISSORS_Y_SHIFT);
- scissor->bottom_right =
- ((state->maxx - 1) << R300_SCISSORS_X_SHIFT) |
- ((state->maxy - 1) << R300_SCISSORS_Y_SHIFT);
- } else {
- /* Offset of 1440 in non-R500 chipsets. */
- scissor->top_left =
- ((state->minx + 1440) << R300_SCISSORS_X_SHIFT) |
- ((state->miny + 1440) << R300_SCISSORS_Y_SHIFT);
- scissor->bottom_right =
- (((state->maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
- (((state->maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
- }
-}
-
static void
r300_set_framebuffer_state(struct pipe_context* pipe,
const struct pipe_framebuffer_state* state)
{
struct r300_context* r300 = r300_context(pipe);
- struct r300_scissor_state* scissor =
- (struct r300_scissor_state*)r300->scissor_state.state;
- struct pipe_scissor_state pscissor;
+ uint32_t zbuffer_bpp = 0;
+
+ r300->fb_state.size = (10 * state->nr_cbufs) +
+ (2 * (4 - state->nr_cbufs)) +
+ (state->zsbuf ? 10 : 0) + 6;
+
+ if (state->nr_cbufs > 4) {
+ debug_printf("r300: Implementation error: Too many MRTs in %s, "
+ "refusing to bind framebuffer state!\n", __FUNCTION__);
+ return;
+ }
if (r300->draw) {
draw_flush(r300->draw);
}
- r300->framebuffer_state = *state;
-
- /* XXX Arg. This is silly. */
- pscissor.minx = pscissor.miny = 0;
- pscissor.maxx = state->width;
- pscissor.maxy = state->height;
- r300_set_scissor_regs(&pscissor, &scissor->framebuffer,
- r300_screen(r300->context.screen)->caps->is_r500);
+ memcpy(r300->fb_state.state, state, sizeof(struct pipe_framebuffer_state));
/* Don't rely on the order of states being set for the first time. */
- r300->dirty_state |= R300_NEW_FRAMEBUFFERS;
-
+ /* XXX wait what */
r300->blend_state.dirty = TRUE;
r300->dsa_state.dirty = TRUE;
+ r300->fb_state.dirty = TRUE;
r300->scissor_state.dirty = TRUE;
+
+ /* Polygon offset depends on the zbuffer bit depth. */
+ if (state->zsbuf && r300->polygon_offset_enabled) {
+ switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
+ case 2:
+ zbuffer_bpp = 16;
+ break;
+ case 4:
+ zbuffer_bpp = 24;
+ break;
+ }
+
+ if (r300->zbuffer_bpp != zbuffer_bpp) {
+ r300->zbuffer_bpp = zbuffer_bpp;
+ r300->rs_state.dirty = TRUE;
+ }
+ }
}
/* Create fragment shader state. */
r300_pick_fragment_shader(r300);
if (r300->vs && r300_vertex_shader_setup_wpos(r300)) {
- r300->dirty_state |= R300_NEW_VERTEX_FORMAT;
+ r300->vertex_format_state.dirty = TRUE;
}
r300->dirty_state |= R300_NEW_FRAGMENT_SHADER | R300_NEW_FRAGMENT_SHADER_CONSTANTS;
rs->line_control = pack_float_16_6x(state->line_width) |
R300_GA_LINE_CNTL_END_TYPE_COMP;
- /* XXX I think there is something wrong with the polygon mode,
- * XXX re-test when r300g is in a better shape */
-
/* Enable polygon mode */
if (state->fill_cw != PIPE_POLYGON_MODE_FILL ||
state->fill_ccw != PIPE_POLYGON_MODE_FILL) {
}
if (rs->polygon_offset_enable) {
- rs->depth_offset_front = rs->depth_offset_back =
- fui(state->offset_units);
- rs->depth_scale_front = rs->depth_scale_back =
- fui(state->offset_scale);
+ rs->depth_offset = state->offset_units;
+ rs->depth_scale = state->offset_scale;
}
if (state->line_stipple_enable) {
draw_set_rasterizer_state(r300->draw, &rs->rs);
}
- r300->tcl_bypass = rs->rs.bypass_vs_clip_and_viewport;
+ if (rs) {
+ r300->tcl_bypass = rs->rs.bypass_vs_clip_and_viewport;
+ r300->polygon_offset_enabled = rs->rs.offset_cw || rs->rs.offset_ccw;
+ } else {
+ r300->tcl_bypass = FALSE;
+ r300->polygon_offset_enabled = FALSE;
+ }
r300->rs_state.state = rs;
r300->rs_state.dirty = TRUE;
r300->viewport_state.dirty = TRUE;
/* XXX Clean these up when we move to atom emits */
- r300->dirty_state |= R300_NEW_RS_BLOCK;
if (r300->fs && r300->fs->inputs.wpos != ATTR_UNUSED) {
r300->dirty_state |= R300_NEW_FRAGMENT_SHADER_CONSTANTS;
}
const struct pipe_scissor_state* state)
{
struct r300_context* r300 = r300_context(pipe);
- struct r300_scissor_state* scissor =
- (struct r300_scissor_state*)r300->scissor_state.state;
- r300_set_scissor_regs(state, &scissor->scissor,
- r300_screen(r300->context.screen)->caps->is_r500);
+ memcpy(r300->scissor_state.state, state,
+ sizeof(struct pipe_scissor_state));
r300->scissor_state.dirty = TRUE;
}
draw_set_vertex_buffers(r300->draw, count, buffers);
}
- r300->dirty_state |= R300_NEW_VERTEX_FORMAT;
+ r300->vertex_format_state.dirty = TRUE;
+}
+
+static boolean r300_validate_aos(struct r300_context *r300)
+{
+ struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
+ struct pipe_vertex_element *velem = r300->vertex_element;
+ int i;
+
+ /* Check if formats and strides are aligned to the size of DWORD. */
+ for (i = 0; i < r300->vertex_element_count; i++) {
+ if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
+ util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
+ return FALSE;
+ }
+ }
+ return TRUE;
}
static void r300_set_vertex_elements(struct pipe_context* pipe,
draw_flush(r300->draw);
draw_set_vertex_elements(r300->draw, count, elements);
}
+
+ if (!r300_validate_aos(r300)) {
+ /* XXX We should fallback using draw. */
+ assert(0);
+ abort();
+ }
}
static void* r300_create_vs_state(struct pipe_context* pipe,
r300_vertex_shader_setup_wpos(r300);
}
+ r300->vertex_format_state.dirty = TRUE;
+
r300->dirty_state |=
- R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS |
- R300_NEW_VERTEX_FORMAT;
+ R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS;
} else {
draw_flush(r300->draw);
draw_bind_vertex_shader(r300->draw,
static void r300_set_constant_buffer(struct pipe_context *pipe,
uint shader, uint index,
- const struct pipe_constant_buffer *buf)
+ struct pipe_buffer *buf)
{
struct r300_context* r300 = r300_context(pipe);
void *mapped;
- if (buf == NULL || buf->buffer->size == 0 ||
- (mapped = pipe_buffer_map(pipe->screen, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ)) == NULL)
+ if (buf == NULL || buf->size == 0 ||
+ (mapped = pipe_buffer_map(pipe->screen, buf, PIPE_BUFFER_USAGE_CPU_READ)) == NULL)
{
r300->shader_constants[shader].count = 0;
return;
}
- assert((buf->buffer->size % 4 * sizeof(float)) == 0);
- memcpy(r300->shader_constants[shader].constants, mapped, buf->buffer->size);
- r300->shader_constants[shader].count = buf->buffer->size / (4 * sizeof(float));
- pipe_buffer_unmap(pipe->screen, buf->buffer);
+ assert((buf->size % 4 * sizeof(float)) == 0);
+ memcpy(r300->shader_constants[shader].constants, mapped, buf->size);
+ r300->shader_constants[shader].count = buf->size / (4 * sizeof(float));
+ pipe_buffer_unmap(pipe->screen, buf);
if (shader == PIPE_SHADER_VERTEX)
r300->dirty_state |= R300_NEW_VERTEX_SHADER_CONSTANTS;
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