#include "pipe/p_shader_tokens.h"
#include "util/u_debug.h"
#include "util/u_memory.h"
+#include "util/u_screen.h"
#include "util/u_simple_shaders.h"
#include "util/u_upload_mgr.h"
#include "util/u_math.h"
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
-#include "radeon/radeon_video.h"
-#include "radeon/radeon_uvd.h"
-#include "os/os_time.h"
+#include "radeon_video.h"
+#include "radeon_uvd.h"
+#include "util/os_time.h"
static const struct debug_named_value r600_debug_options[] = {
/* features */
static void r600_destroy_context(struct pipe_context *context)
{
struct r600_context *rctx = (struct r600_context *)context;
- unsigned sh;
+ unsigned sh, i;
r600_isa_destroy(rctx->isa);
r600_sb_context_destroy(rctx->sb_context);
+ for (sh = 0; sh < (rctx->b.chip_class < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) {
+ r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL);
+ }
r600_resource_reference(&rctx->dummy_cmask, NULL);
r600_resource_reference(&rctx->dummy_fmask, NULL);
+ if (rctx->append_fence)
+ pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
free(rctx->driver_consts[sh].constants);
}
util_unreference_framebuffer_state(&rctx->framebuffer.state);
+ if (rctx->gs_rings.gsvs_ring.buffer)
+ pipe_resource_reference(&rctx->gs_rings.gsvs_ring.buffer, NULL);
+
+ if (rctx->gs_rings.esgs_ring.buffer)
+ pipe_resource_reference(&rctx->gs_rings.esgs_ring.buffer, NULL);
+
+ for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh)
+ for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i)
+ rctx->b.b.set_constant_buffer(context, sh, i, NULL);
+
if (rctx->blitter) {
util_blitter_destroy(rctx->blitter);
}
goto fail;
rctx->screen = rscreen;
- LIST_INITHEAD(&rctx->texture_buffers);
+ list_inithead(&rctx->texture_buffers);
r600_init_blit_functions(rctx);
rctx->b.family == CHIP_CAICOS ||
rctx->b.family == CHIP_CAYMAN ||
rctx->b.family == CHIP_ARUBA);
+
+ rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_DEFAULT, 32);
break;
default:
R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
}
rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
- r600_context_gfx_flush, rctx);
+ r600_context_gfx_flush, rctx, false);
rctx->b.gfx.flush = r600_context_gfx_flush;
rctx->allocator_fetch_shader =
return NULL;
}
+static bool is_nir_enabled(struct r600_common_screen *screen) {
+ return (screen->debug_flags & DBG_NIR &&
+ screen->family >= CHIP_CEDAR &&
+ screen->family < CHIP_CAYMAN);
+}
+
/*
* pipe_screen
*/
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
- case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
case PIPE_CAP_OCCLUSION_QUERY:
- case PIPE_CAP_TEXTURE_SHADOW_MAP:
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
+ case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
- case PIPE_CAP_SM3:
+ case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
+ case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
+ case PIPE_CAP_VERTEX_SHADER_SATURATE:
case PIPE_CAP_SEAMLESS_CUBE_MAP:
case PIPE_CAP_PRIMITIVE_RESTART:
+ case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
case PIPE_CAP_CONDITIONAL_RENDER:
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_USER_CONSTANT_BUFFERS:
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+ case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
return 1;
+ case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
+ /* Optimal number for good TexSubImage performance on Polaris10. */
+ return 64 * 1024 * 1024;
+
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
+ return rscreen->b.info.drm_minor >= 43;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
return rscreen->b.chip_class > R700;
case PIPE_CAP_TGSI_TEXCOORD:
- return 0;
+ return 1;
+ case PIPE_CAP_NIR_IMAGES_AS_DEREF:
case PIPE_CAP_FAKE_SW_MSAA:
return 0;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
if (family >= CHIP_CEDAR)
- return 410;
+ return 430;
/* pre-evergreen geom shaders need newer kernel */
if (rscreen->b.info.drm_minor >= 37)
return 330;
return 140;
+ case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
+ return 140;
+
/* Supported except the original R600. */
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
+ case PIPE_CAP_TGSI_CLOCK:
+ case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
+ case PIPE_CAP_QUERY_BUFFER_OBJECT:
return family >= CHIP_CEDAR ? 1 : 0;
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return family >= CHIP_CEDAR ? 4 : 0;
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
return family >= CHIP_CEDAR ? 0 : 1;
- /* Unsupported features. */
- case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
- case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
- case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
- case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
- case PIPE_CAP_VERTEX_COLOR_CLAMPED:
- case PIPE_CAP_USER_VERTEX_BUFFERS:
- case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
- case PIPE_CAP_VERTEXID_NOBASE:
- case PIPE_CAP_DEPTH_BOUNDS_TEST:
- case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
- case PIPE_CAP_SHAREABLE_SHADERS:
- case PIPE_CAP_DRAW_PARAMETERS:
- case PIPE_CAP_MULTI_DRAW_INDIRECT:
- case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
- case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
- case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
- case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
- case PIPE_CAP_GENERATE_MIPMAP:
- case PIPE_CAP_STRING_MARKER:
- case PIPE_CAP_QUERY_BUFFER_OBJECT:
- case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
- case PIPE_CAP_CULL_DISTANCE:
- case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
- case PIPE_CAP_TGSI_VOTE:
- case PIPE_CAP_MAX_WINDOW_RECTANGLES:
- case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
- case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
- case PIPE_CAP_NATIVE_FENCE_FD:
+ case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+ return 8;
+
+ case PIPE_CAP_MAX_GS_INVOCATIONS:
+ return 32;
+
+ /* shader buffer objects */
+ case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
+ return 1 << 27;
+ case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
+ return 8;
+
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
- case PIPE_CAP_TGSI_FS_FBFETCH:
- case PIPE_CAP_INT64:
- case PIPE_CAP_INT64_DIVMOD:
- case PIPE_CAP_TGSI_TEX_TXF_LZ:
- case PIPE_CAP_TGSI_CLOCK:
- case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
- case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
- case PIPE_CAP_TGSI_BALLOT:
- case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
- case PIPE_CAP_POST_DEPTH_COVERAGE:
- case PIPE_CAP_BINDLESS_TEXTURE:
return 0;
case PIPE_CAP_DOUBLES:
rscreen->b.family == CHIP_HEMLOCK)
return 1;
return 0;
+ case PIPE_CAP_CULL_DISTANCE:
+ return 1;
+
+ case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
+ if (family >= CHIP_CEDAR)
+ return 256;
+ return 0;
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
if (family >= CHIP_CEDAR)
return family >= CHIP_CEDAR ? 4 : 1;
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
- return 2047;
+ /* Should be 2047, but 2048 is a requirement for GL 4.4 */
+ return 2048;
/* Texturing. */
- case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+ case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
+ if (family >= CHIP_CEDAR)
+ return 16384;
+ else
+ return 8192;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
if (family >= CHIP_CEDAR)
return 15;
case PIPE_CAP_MAX_VIEWPORTS:
return R600_MAX_VIEWPORTS;
case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
+ case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
return 8;
/* Timer queries, present when the clock frequency is non zero. */
case PIPE_CAP_MAX_TEXEL_OFFSET:
return 7;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 32;
+
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
case PIPE_CAP_ENDIANNESS:
return rscreen->b.info.pci_dev;
case PIPE_CAP_PCI_FUNCTION:
return rscreen->b.info.pci_func;
+
+ case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
+ if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
+ return 8;
+ return 0;
+ case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
+ if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
+ return EG_MAX_ATOMIC_BUFFERS;
+ return 0;
+
+ default:
+ return u_pipe_screen_get_param_defaults(pscreen, param);
}
- return 0;
}
static int r600_get_shader_param(struct pipe_screen* pscreen,
{
case PIPE_SHADER_FRAGMENT:
case PIPE_SHADER_VERTEX:
- case PIPE_SHADER_COMPUTE:
break;
case PIPE_SHADER_GEOMETRY:
if (rscreen->b.family >= CHIP_CEDAR)
if (rscreen->b.info.drm_minor >= 37)
break;
return 0;
+ /* With NIR we currently disable TES, TCS and COMP shaders */
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
if (rscreen->b.family >= CHIP_CEDAR)
break;
+ /* fallthrough */
+ case PIPE_SHADER_COMPUTE:
+ if (!is_nir_enabled(&rscreen->b))
+ break;
+ /* fallthrough */
default:
return 0;
}
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
if (shader == PIPE_SHADER_COMPUTE) {
uint64_t max_const_buffer_size;
- pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
- PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
- &max_const_buffer_size);
+ enum pipe_shader_ir ir_type = is_nir_enabled(&rscreen->b) ?
+ PIPE_SHADER_IR_NIR: PIPE_SHADER_IR_TGSI;
+ pscreen->get_compute_param(pscreen, ir_type,
+ PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
+ &max_const_buffer_size);
return MIN2(max_const_buffer_size, INT_MAX);
} else {
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
+ case PIPE_SHADER_CAP_INT64_ATOMICS:
+ case PIPE_SHADER_CAP_FP16:
+ case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+ case PIPE_SHADER_CAP_INT16:
+ case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
return 0;
case PIPE_SHADER_CAP_INTEGERS:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 16;
- case PIPE_SHADER_CAP_PREFERRED_IR:
- if (shader == PIPE_SHADER_COMPUTE) {
- return PIPE_SHADER_IR_NATIVE;
- } else {
- return PIPE_SHADER_IR_TGSI;
+ case PIPE_SHADER_CAP_PREFERRED_IR:
+ if (is_nir_enabled(&rscreen->b))
+ return PIPE_SHADER_IR_NIR;
+ return PIPE_SHADER_IR_TGSI;
+ case PIPE_SHADER_CAP_SUPPORTED_IRS: {
+ int ir = 0;
+ if (shader == PIPE_SHADER_COMPUTE)
+ ir = 1 << PIPE_SHADER_IR_NATIVE;
+ if (rscreen->b.family >= CHIP_CEDAR) {
+ ir |= 1 << PIPE_SHADER_IR_TGSI;
+ if (is_nir_enabled(&rscreen->b))
+ ir |= 1 << PIPE_SHADER_IR_NIR;
}
- case PIPE_SHADER_CAP_SUPPORTED_IRS:
- return 0;
+ return ir;
+ }
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
if (rscreen->b.family == CHIP_ARUBA ||
rscreen->b.family == CHIP_CAYMAN ||
return 0;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
- case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
- case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
+ case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
+ case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
+ case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
+ if (rscreen->b.family >= CHIP_CEDAR &&
+ (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
+ return 8;
+ return 0;
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+ if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
+ return 8;
+ return 0;
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+ /* having to allocate the atomics out amongst shaders stages is messy,
+ so give compute 8 buffers and all the others one */
+ if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
+ return EG_MAX_ATOMIC_BUFFERS;
+ }
+ return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
/* due to a bug in the shader compiler, some loops hang
* if they are not unrolled, see:
return r600_resource_create_common(screen, templ);
}
-struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
+struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
+ const struct pipe_screen_config *config)
{
struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
rscreen->b.debug_flags |= DBG_COMPUTE;
if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
- rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS | DBG_TCS | DBG_TES;
+ rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
if (!debug_get_bool_option("R600_HYPERZ", TRUE))
rscreen->b.debug_flags |= DBG_NO_HYPERZ;
R600_CONTEXT_INV_VERTEX_CACHE |
R600_CONTEXT_INV_TEX_CACHE |
R600_CONTEXT_INV_CONST_CACHE;
- rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_PS_PARTIAL_FLUSH;
+ rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
rscreen->global_pool = compute_memory_pool_new(rscreen);
/* Create the auxiliary context. This must be done last. */
rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
+ rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
#if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
struct pipe_resource templ = {};
projects / mesa.git / blobdiff