#include "r600_formats.h"
#include "r600_opcodes.h"
#include "r600_shader.h"
+#include "r600_dump.h"
#include "r600d.h"
+#include "sfn/sfn_nir.h"
#include "sb/sb_public.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_scan.h"
#include "tgsi/tgsi_dump.h"
+#include "tgsi/tgsi_from_mesa.h"
+#include "nir/tgsi_to_nir.h"
+#include "nir/nir_to_tgsi_info.h"
+#include "compiler/nir/nir.h"
#include "util/u_bitcast.h"
#include "util/u_memory.h"
#include "util/u_math.h"
if (shader->bo == NULL) {
return -ENOMEM;
}
- ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
+ ptr = r600_buffer_map_sync_with_rings(
+ &rctx->b, shader->bo,
+ PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
if (R600_BIG_ENDIAN) {
for (i = 0; i < shader->shader.bc.ndw; ++i) {
ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
return 0;
}
+extern const struct nir_shader_compiler_options r600_nir_options;
+static int nshader = 0;
int r600_pipe_shader_create(struct pipe_context *ctx,
struct r600_pipe_shader *shader,
union r600_shader_key key)
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_shader_selector *sel = shader->selector;
int r;
- bool dump = r600_can_dump_shader(&rctx->screen->b,
- tgsi_get_processor_type(sel->tokens));
- unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
- unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
+ struct r600_screen *rscreen = (struct r600_screen *)ctx->screen;
+
+ int processor = sel->ir_type == PIPE_SHADER_IR_TGSI ?
+ tgsi_get_processor_type(sel->tokens):
+ pipe_shader_type_from_mesa(sel->nir->info.stage);
+
+ bool dump = r600_can_dump_shader(&rctx->screen->b, processor);
+ unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB) &&
+ !(rscreen->b.debug_flags & DBG_NIR);
+ unsigned sb_disasm;
unsigned export_shader;
-
+
shader->shader.bc.isa = rctx->isa;
+
+ if (!(rscreen->b.debug_flags & DBG_NIR)) {
+ assert(sel->ir_type == PIPE_SHADER_IR_TGSI);
+ r = r600_shader_from_tgsi(rctx, shader, key);
+ if (r) {
+ R600_ERR("translation from TGSI failed !\n");
+ goto error;
+ }
+ } else {
+ if (sel->ir_type == PIPE_SHADER_IR_TGSI) {
+ sel->nir = tgsi_to_nir(sel->tokens, ctx->screen, true);
+ /* Lower int64 ops because we have some r600 build-in shaders that use it */
+ if (!ctx->screen->get_param(ctx->screen, PIPE_CAP_DOUBLES)) {
+ NIR_PASS_V(sel->nir, nir_lower_regs_to_ssa);
+ NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar, NULL, NULL);
+ NIR_PASS_V(sel->nir, nir_lower_int64, ~0);
+ NIR_PASS_V(sel->nir, nir_opt_vectorize);
+ }
+ NIR_PASS_V(sel->nir, nir_lower_flrp, ~0, false, false);
+ }
+ nir_tgsi_scan_shader(sel->nir, &sel->info, true);
+ r = r600_shader_from_nir(rctx, shader, &key);
+ if (r) {
+ fprintf(stderr, "--Failed shader--------------------------------------------------\n");
+
+ if (sel->ir_type == PIPE_SHADER_IR_TGSI) {
+ fprintf(stderr, "--TGSI--------------------------------------------------------\n");
+ tgsi_dump(sel->tokens, 0);
+ }
+
+ if (rscreen->b.debug_flags & DBG_NIR) {
+ fprintf(stderr, "--NIR --------------------------------------------------------\n");
+ nir_print_shader(sel->nir, stderr);
+ }
+
+ R600_ERR("translation from NIR failed !\n");
+ goto error;
+ }
+ }
+
if (dump) {
- fprintf(stderr, "--------------------------------------------------------------\n");
- tgsi_dump(sel->tokens, 0);
-
+ if (sel->ir_type == PIPE_SHADER_IR_TGSI) {
+ fprintf(stderr, "--TGSI--------------------------------------------------------\n");
+ tgsi_dump(sel->tokens, 0);
+ }
+
if (sel->so.num_outputs) {
r600_dump_streamout(&sel->so);
}
}
- r = r600_shader_from_tgsi(rctx, shader, key);
- if (r) {
- R600_ERR("translation from TGSI failed !\n");
- goto error;
- }
+
if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
/* only disable for vertex shaders in tess paths */
if (key.vs.as_ls)
}
}
+ sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
if (dump && !sb_disasm) {
fprintf(stderr, "--------------------------------------------------------------\n");
r600_bytecode_disasm(&shader->shader.bc);
fprintf(stderr, "______________________________________________________________\n");
} else if ((dump && sb_disasm) || use_sb) {
- r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
+ r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
dump, use_sb);
if (r) {
R600_ERR("r600_sb_bytecode_process failed !\n");
}
}
+ if (dump) {
+ FILE *f;
+ char fname[1024];
+ snprintf(fname, 1024, "shader_from_%s_%d.cpp",
+ (sel->ir_type == PIPE_SHADER_IR_TGSI ?
+ (rscreen->b.debug_flags & DBG_NIR ? "tgsi-nir" : "tgsi")
+ : "nir"), nshader);
+ f = fopen(fname, "w");
+ print_shader_info(f, nshader++, &shader->shader);
+ print_shader_info(stderr, nshader++, &shader->shader);
+ print_pipe_info(stderr, &sel->info);
+ if (sel->ir_type == PIPE_SHADER_IR_TGSI) {
+ fprintf(f, "/****TGSI**********************************\n");
+ tgsi_dump_to_file(sel->tokens, 0, f);
+ }
+
+ if (rscreen->b.debug_flags & DBG_NIR){
+ fprintf(f, "/****NIR **********************************\n");
+ nir_print_shader(sel->nir, f);
+ }
+ fprintf(f, "******************************************/\n");
+ fclose(f);
+ }
+
if (shader->gs_copy_shader) {
if (dump) {
// dump copy shader
void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
{
r600_resource_reference(&shader->bo, NULL);
- r600_bytecode_clear(&shader->shader.bc);
+ if (shader->shader.bc.cf.next)
+ r600_bytecode_clear(&shader->shader.bc);
r600_release_command_buffer(&shader->command_buffer);
}
struct r600_shader_ctx {
struct tgsi_shader_info info;
+ struct tgsi_array_info *array_infos;
+ /* flag for each tgsi temp array if its been spilled or not */
+ bool *spilled_arrays;
struct tgsi_parse_context parse;
const struct tgsi_token *tokens;
unsigned type;
unsigned tess_input_info; /* temp with tess input offsets */
unsigned tess_output_info; /* temp with tess input offsets */
unsigned thread_id_gpr; /* temp with thread id calculated for images */
- bool thread_id_gpr_loaded;
};
struct r600_shader_tgsi_instruction {
static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
-static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
+static inline int callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
static int tgsi_else(struct r600_shader_ctx *ctx);
static int tgsi_endif(struct r600_shader_ctx *ctx);
static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
unsigned dst_reg, unsigned mask);
+static bool ctx_needs_stack_workaround_8xx(struct r600_shader_ctx *ctx)
+{
+ if (ctx->bc->family == CHIP_HEMLOCK ||
+ ctx->bc->family == CHIP_CYPRESS ||
+ ctx->bc->family == CHIP_JUNIPER)
+ return false;
+ return true;
+}
+
static int tgsi_last_instruction(unsigned writemask)
{
int i, lasti = 0;
#endif
for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
if (i->Src[j].Register.Dimension) {
- switch (i->Src[j].Register.File) {
- case TGSI_FILE_CONSTANT:
- case TGSI_FILE_HW_ATOMIC:
- break;
- case TGSI_FILE_INPUT:
- if (ctx->type == PIPE_SHADER_GEOMETRY ||
- ctx->type == PIPE_SHADER_TESS_CTRL ||
- ctx->type == PIPE_SHADER_TESS_EVAL)
- break;
- case TGSI_FILE_OUTPUT:
- if (ctx->type == PIPE_SHADER_TESS_CTRL)
- break;
- default:
- R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
- i->Src[j].Register.File,
- i->Src[j].Register.Dimension);
- return -EINVAL;
- }
+ switch (i->Src[j].Register.File) {
+ case TGSI_FILE_CONSTANT:
+ case TGSI_FILE_HW_ATOMIC:
+ break;
+ case TGSI_FILE_INPUT:
+ if (ctx->type == PIPE_SHADER_GEOMETRY ||
+ ctx->type == PIPE_SHADER_TESS_CTRL ||
+ ctx->type == PIPE_SHADER_TESS_EVAL)
+ break;
+ /* fallthrough */
+ case TGSI_FILE_OUTPUT:
+ if (ctx->type == PIPE_SHADER_TESS_CTRL)
+ break;
+ /* fallthrough */
+ default:
+ R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
+ i->Src[j].Register.File,
+ i->Src[j].Register.Dimension);
+ return -EINVAL;
+ }
}
}
for (j = 0; j < i->Instruction.NumDstRegs; j++) {
else {
if (name == TGSI_SEMANTIC_GENERIC) {
/* For generic params simply use sid from tgsi */
+ index = 9 + io->sid;
+ } else if (name == TGSI_SEMANTIC_TEXCOORD) {
index = io->sid;
} else {
/* For non-generic params - pack name and sid into 8 bits */
case TGSI_SEMANTIC_CLIPDIST:
assert(index <= 1);
return 2 + index;
+ case TGSI_SEMANTIC_TEXCOORD:
+ return 4 + index;
case TGSI_SEMANTIC_GENERIC:
if (index <= 63-4)
- return 4 + index - 9;
+ return 4 + index;
else
/* same explanation as in the default statement,
* the only user hitting this is st/nine.
return 0;
}
+static void choose_spill_arrays(struct r600_shader_ctx *ctx, int *regno, unsigned *scratch_space_needed)
+{
+ // pick largest array and spill it, repeat until the number of temps is under limit or we run out of arrays
+ unsigned n = ctx->info.array_max[TGSI_FILE_TEMPORARY];
+ unsigned narrays_left = n;
+ bool *spilled = ctx->spilled_arrays; // assumed calloc:ed
+
+ *scratch_space_needed = 0;
+ while (*regno > 124 && narrays_left) {
+ unsigned i;
+ unsigned largest = 0;
+ unsigned largest_index = 0;
+
+ for (i = 0; i < n; i++) {
+ unsigned size = ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
+ if (!spilled[i] && size > largest) {
+ largest = size;
+ largest_index = i;
+ }
+ }
+
+ spilled[largest_index] = true;
+ *regno -= largest;
+ *scratch_space_needed += largest;
+
+ narrays_left --;
+ }
+
+ if (narrays_left == 0) {
+ ctx->info.indirect_files &= ~(1 << TGSI_FILE_TEMPORARY);
+ }
+}
+
+/* Take spilled temp arrays into account when translating tgsi register
+ * indexes into r600 gprs if spilled is false, or scratch array offset if
+ * spilled is true */
+static int map_tgsi_reg_index_to_r600_gpr(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index, bool *spilled)
+{
+ unsigned i;
+ unsigned spilled_size = 0;
+
+ for (i = 0; i < ctx->info.array_max[TGSI_FILE_TEMPORARY]; i++) {
+ if (tgsi_reg_index >= ctx->array_infos[i].range.First && tgsi_reg_index <= ctx->array_infos[i].range.Last) {
+ if (ctx->spilled_arrays[i]) {
+ /* vec4 index into spilled scratch memory */
+ *spilled = true;
+ return tgsi_reg_index - ctx->array_infos[i].range.First + spilled_size;
+ }
+ else {
+ /* regular GPR array */
+ *spilled = false;
+ return tgsi_reg_index - spilled_size + ctx->file_offset[TGSI_FILE_TEMPORARY];
+ }
+ }
+
+ if (tgsi_reg_index < ctx->array_infos[i].range.First)
+ break;
+ if (ctx->spilled_arrays[i]) {
+ spilled_size += ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
+ }
+ }
+
+ /* regular GPR index, minus the holes from spilled arrays */
+ *spilled = false;
+
+ return tgsi_reg_index - spilled_size + ctx->file_offset[TGSI_FILE_TEMPORARY];
+}
+
+/* look up spill area base offset and array size for a spilled temp array */
+static void get_spilled_array_base_and_size(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index,
+ unsigned *array_base, unsigned *array_size)
+{
+ unsigned i;
+ unsigned offset = 0;
+
+ for (i = 0; i < ctx->info.array_max[TGSI_FILE_TEMPORARY]; i++) {
+ if (ctx->spilled_arrays[i]) {
+ unsigned size = ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
+
+ if (tgsi_reg_index >= ctx->array_infos[i].range.First && tgsi_reg_index <= ctx->array_infos[i].range.Last) {
+ *array_base = offset;
+ *array_size = size - 1; /* hw counts from 1 */
+
+ return;
+ }
+
+ offset += size;
+ }
+ }
+}
+
static int tgsi_declaration(struct r600_shader_ctx *ctx)
{
struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
case TGSI_FILE_TEMPORARY:
if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
if (d->Array.ArrayID) {
- r600_add_gpr_array(ctx->shader,
- ctx->file_offset[TGSI_FILE_TEMPORARY] +
- d->Range.First,
- d->Range.Last - d->Range.First + 1, 0x0F);
+ bool spilled;
+ unsigned idx = map_tgsi_reg_index_to_r600_gpr(ctx,
+ d->Range.First,
+ &spilled);
+
+ if (!spilled) {
+ r600_add_gpr_array(ctx->shader, idx,
+ d->Range.Last - d->Range.First + 1, 0x0F);
+ }
}
}
break;
if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
location = TGSI_INTERPOLATE_LOC_CENTER;
- inputs[1].enabled = true; /* needs SAMPLEID */
} else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
location = TGSI_INTERPOLATE_LOC_CENTER;
/* Needs sample positions, currently those are always available */
tgsi_parse_free(&parse);
+ if (ctx->info.reads_samplemask &&
+ (ctx->info.uses_linear_sample || ctx->info.uses_persp_sample)) {
+ inputs[1].enabled = true;
+ }
+
+ if (ctx->bc->chip_class >= EVERGREEN) {
+ int num_baryc = 0;
+ /* assign gpr to each interpolator according to priority */
+ for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
+ if (ctx->eg_interpolators[i].enabled) {
+ ctx->eg_interpolators[i].ij_index = num_baryc;
+ num_baryc++;
+ }
+ }
+ num_baryc = (num_baryc + 1) >> 1;
+ gpr_offset += num_baryc;
+ }
+
for (i = 0; i < ARRAY_SIZE(inputs); i++) {
boolean enabled = inputs[i].enabled;
int *reg = inputs[i].reg;
* for evergreen we need to scan the shader to find the number of GPRs we need to
* reserve for interpolation and system values
*
- * we need to know if we are going to emit
- * any sample or centroid inputs
+ * we need to know if we are going to emit any sample or centroid inputs
* if perspective and linear are required
*/
static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
{
unsigned i;
- int num_baryc;
- struct tgsi_parse_context parse;
memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
+ /*
+ * Could get this information from the shader info. But right now
+ * we interpolate all declared inputs, whereas the shader info will
+ * only contain the bits if the inputs are actually used, so it might
+ * not be safe...
+ */
for (i = 0; i < ctx->info.num_inputs; i++) {
int k;
/* skip position/face/mask/sampleid */
ctx->eg_interpolators[k].enabled = TRUE;
}
- if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
- return 0;
- }
-
- /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
- while (!tgsi_parse_end_of_tokens(&parse)) {
- tgsi_parse_token(&parse);
-
- if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
- const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
- if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
- inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
- inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
- {
- int interpolate, location, k;
-
- if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
- location = TGSI_INTERPOLATE_LOC_CENTER;
- } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
- location = TGSI_INTERPOLATE_LOC_CENTER;
- } else {
- location = TGSI_INTERPOLATE_LOC_CENTROID;
- }
-
- interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
- k = eg_get_interpolator_index(interpolate, location);
- if (k >= 0)
- ctx->eg_interpolators[k].enabled = true;
- }
- }
- }
-
- tgsi_parse_free(&parse);
-
- /* assign gpr to each interpolator according to priority */
- num_baryc = 0;
- for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
- if (ctx->eg_interpolators[i].enabled) {
- ctx->eg_interpolators[i].ij_index = num_baryc;
- num_baryc ++;
- }
- }
-
/* XXX PULL MODEL and LINE STIPPLE */
- num_baryc = (num_baryc + 1) >> 1;
- return allocate_system_value_inputs(ctx, num_baryc);
+ return allocate_system_value_inputs(ctx, 0);
}
/* sample_id_sel == NULL means fetch for current sample */
struct r600_bytecode_vtx vtx;
int r, t1;
- assert(ctx->fixed_pt_position_gpr != -1);
-
t1 = r600_get_temp(ctx);
memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
if (sample_id == NULL) {
+ assert(ctx->fixed_pt_position_gpr != -1);
+
vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
vtx.src_sel_x = 3;
}
r600_src->neg = tgsi_src->Register.Negate;
r600_src->abs = tgsi_src->Register.Absolute;
+ if (tgsi_src->Register.File == TGSI_FILE_TEMPORARY) {
+ bool spilled;
+ unsigned idx;
+
+ idx = map_tgsi_reg_index_to_r600_gpr(ctx, tgsi_src->Register.Index, &spilled);
+
+ if (spilled) {
+ int reg = r600_get_temp(ctx);
+ int r;
+
+ r600_src->sel = reg;
+
+ if (ctx->bc->chip_class < R700) {
+ struct r600_bytecode_output cf;
+
+ memset(&cf, 0, sizeof(struct r600_bytecode_output));
+ cf.op = CF_OP_MEM_SCRATCH;
+ cf.elem_size = 3;
+ cf.gpr = reg;
+ cf.comp_mask = 0xF;
+ cf.swizzle_x = 0;
+ cf.swizzle_y = 1;
+ cf.swizzle_z = 2;
+ cf.swizzle_w = 3;
+ cf.burst_count = 1;
+
+ get_spilled_array_base_and_size(ctx, tgsi_src->Register.Index,
+ &cf.array_base, &cf.array_size);
+
+ if (tgsi_src->Register.Indirect) {
+ cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
+ cf.index_gpr = ctx->bc->ar_reg;
+ }
+ else {
+ cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ;
+ cf.array_base += idx;
+ cf.array_size = 0;
+ }
+
+ r = r600_bytecode_add_output(ctx->bc, &cf);
+ }
+ else {
+ struct r600_bytecode_vtx vtx;
+
+ if (r600_bytecode_get_need_wait_ack(ctx->bc)) {
+ r600_bytecode_need_wait_ack(ctx->bc, false);
+ r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
+ }
+
+ memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
+ vtx.op = FETCH_OP_READ_SCRATCH;
+ vtx.dst_gpr = reg;
+ vtx.uncached = 1; // Must bypass cache since prior spill written in same invocation
+ vtx.elem_size = 3;
+ vtx.data_format = FMT_32_32_32_32;
+ vtx.num_format_all = V_038010_SQ_NUM_FORMAT_INT;
+ vtx.dst_sel_x = tgsi_src->Register.SwizzleX;
+ vtx.dst_sel_y = tgsi_src->Register.SwizzleY;
+ vtx.dst_sel_z = tgsi_src->Register.SwizzleZ;
+ vtx.dst_sel_w = tgsi_src->Register.SwizzleW;
+
+ get_spilled_array_base_and_size(ctx, tgsi_src->Register.Index,
+ &vtx.array_base, &vtx.array_size);
+
+ if (tgsi_src->Register.Indirect) {
+ vtx.indexed = 1;
+ vtx.src_gpr = ctx->bc->ar_reg;
+ }
+ else {
+ vtx.array_base += idx;
+ vtx.array_size = 0;
+ }
+
+ r = r600_bytecode_add_vtx(ctx->bc, &vtx);
+ }
+
+ if (r)
+ return;
+ }
+ else {
+ if (tgsi_src->Register.Indirect)
+ r600_src->rel = V_SQ_REL_RELATIVE;
+
+ r600_src->sel = idx;
+ }
+
+ return;
+ }
+
if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
int index;
if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
} else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
r600_src->sel = 2;
} else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
- if (ctx->type == PIPE_SHADER_TESS_CTRL) {
- r600_src->sel = ctx->tess_input_info;
- r600_src->swizzle[0] = 2;
- r600_src->swizzle[1] = 2;
- r600_src->swizzle[2] = 2;
- r600_src->swizzle[3] = 2;
- } else {
- r600_src->sel = ctx->tess_input_info;
- r600_src->swizzle[0] = 3;
- r600_src->swizzle[1] = 3;
- r600_src->swizzle[2] = 3;
- r600_src->swizzle[3] = 3;
- }
+ r600_src->sel = ctx->tess_input_info;
+ r600_src->swizzle[0] = 2;
+ r600_src->swizzle[1] = 2;
+ r600_src->swizzle[2] = 2;
+ r600_src->swizzle[3] = 2;
} else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
r600_src->sel = 0;
r600_src->swizzle[0] = 0;
r600_bytecode_add_alu(ctx->bc, &alu);
}
-static int generate_gs_copy_shader(struct r600_context *rctx,
- struct r600_pipe_shader *gs,
- struct pipe_stream_output_info *so)
+int generate_gs_copy_shader(struct r600_context *rctx,
+ struct r600_pipe_shader *gs,
+ struct pipe_stream_output_info *so)
{
struct r600_shader_ctx ctx = {};
struct r600_shader *gs_shader = &gs->shader;
for (i = 0; i < ctx->shader->noutput; i++) {
struct r600_bytecode_alu alu;
- int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
+ int param = r600_get_lds_unique_index(ctx->shader->output[i].name,
+ ctx->shader->output[i].sid);
if (param) {
r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
struct r600_bytecode_alu alu;
int r;
- if (ctx->thread_id_gpr_loaded)
- return 0;
-
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
alu.dst.sel = ctx->temp_reg;
ctx->temp_reg, 0);
if (r)
return r;
- ctx->thread_id_gpr_loaded = true;
return 0;
}
tgsi_scan_shader(tokens, &ctx.info);
shader->indirect_files = ctx.info.indirect_files;
+ int narrays = ctx.info.array_max[TGSI_FILE_TEMPORARY];
+ ctx.array_infos = calloc(narrays, sizeof(*ctx.array_infos));
+ ctx.spilled_arrays = calloc(narrays, sizeof(bool));
+ tgsi_scan_arrays(tokens, TGSI_FILE_TEMPORARY, narrays, ctx.array_infos);
+
shader->uses_helper_invocation = false;
shader->uses_doubles = ctx.info.uses_doubles;
shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
ctx.gs_next_vertex = 0;
ctx.gs_stream_output_info = &so;
+ ctx.thread_id_gpr = -1;
ctx.face_gpr = -1;
ctx.fixed_pt_position_gpr = -1;
ctx.fragcoord_input = -1;
ctx.colors_used = 0;
ctx.clip_vertex_write = 0;
- ctx.thread_id_gpr_loaded = false;
ctx.helper_invoc_reg = -1;
ctx.cs_block_size_reg = -1;
/* Outside the GPR range. This will be translated to one of the
* kcache banks later. */
ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
-
ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
- ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
- ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
- ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
- ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
+
+ pipeshader->scratch_space_needed = 0;
+ int regno = ctx.file_offset[TGSI_FILE_TEMPORARY] +
+ ctx.info.file_max[TGSI_FILE_TEMPORARY];
+ if (regno > 124) {
+ choose_spill_arrays(&ctx, ®no, &pipeshader->scratch_space_needed);
+ shader->indirect_files = ctx.info.indirect_files;
+ }
+ shader->needs_scratch_space = pipeshader->scratch_space_needed != 0;
+
+ ctx.bc->ar_reg = ++regno;
+ ctx.bc->index_reg[0] = ++regno;
+ ctx.bc->index_reg[1] = ++regno;
if (ctx.type == PIPE_SHADER_TESS_CTRL) {
- ctx.tess_input_info = ctx.bc->ar_reg + 3;
- ctx.tess_output_info = ctx.bc->ar_reg + 4;
- ctx.temp_reg = ctx.bc->ar_reg + 5;
+ ctx.tess_input_info = ++regno;
+ ctx.tess_output_info = ++regno;
} else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
- ctx.tess_input_info = 0;
- ctx.tess_output_info = ctx.bc->ar_reg + 3;
- ctx.temp_reg = ctx.bc->ar_reg + 4;
+ ctx.tess_input_info = ++regno;
+ ctx.tess_output_info = ++regno;
} else if (ctx.type == PIPE_SHADER_GEOMETRY) {
- ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
- ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
- ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
- ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
- ctx.temp_reg = ctx.bc->ar_reg + 7;
+ ctx.gs_export_gpr_tregs[0] = ++regno;
+ ctx.gs_export_gpr_tregs[1] = ++regno;
+ ctx.gs_export_gpr_tregs[2] = ++regno;
+ ctx.gs_export_gpr_tregs[3] = ++regno;
if (ctx.shader->gs_tri_strip_adj_fix) {
- ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
- ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
- ctx.temp_reg += 2;
+ ctx.gs_rotated_input[0] = ++regno;
+ ctx.gs_rotated_input[1] = ++regno;
} else {
ctx.gs_rotated_input[0] = 0;
ctx.gs_rotated_input[1] = 1;
}
- } else {
- ctx.temp_reg = ctx.bc->ar_reg + 3;
}
if (shader->uses_images) {
- ctx.thread_id_gpr = ctx.temp_reg++;
- ctx.thread_id_gpr_loaded = false;
+ ctx.thread_id_gpr = ++regno;
}
+ ctx.temp_reg = ++regno;
shader->max_arrays = 0;
shader->num_arrays = 0;
if (shader->vs_as_gs_a)
vs_add_primid_output(&ctx, key.vs.prim_id_out);
+ if (ctx.thread_id_gpr != -1) {
+ r = load_thread_id_gpr(&ctx);
+ if (r)
+ return r;
+ }
+
if (ctx.type == PIPE_SHADER_TESS_EVAL)
r600_fetch_tess_io_info(&ctx);
r = eg_load_helper_invocation(&ctx);
if (r)
return r;
+ }
+ /*
+ * XXX this relies on fixed_pt_position_gpr only being present when
+ * this shader should be executed per sample. Should be the case for now...
+ */
+ if (ctx.fixed_pt_position_gpr != -1 && ctx.info.reads_samplemask) {
+ /*
+ * Fix up sample mask. The hw always gives us coverage mask for
+ * the pixel. However, for per-sample shading, we need the
+ * coverage for the shader invocation only.
+ * Also, with disabled msaa, only the first bit should be set
+ * (luckily the same fixup works for both problems).
+ * For now, we can only do it if we know this shader is always
+ * executed per sample (due to usage of bits in the shader
+ * forcing per-sample execution).
+ * If the fb is not multisampled, we'd do unnecessary work but
+ * it should still be correct.
+ * It will however do nothing for sample shading according
+ * to MinSampleShading.
+ */
+ struct r600_bytecode_alu alu;
+ int tmp = r600_get_temp(&ctx);
+ assert(ctx.face_gpr != -1);
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+
+ alu.op = ALU_OP2_LSHL_INT;
+ alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.src[0].value = 0x1;
+ alu.src[1].sel = ctx.fixed_pt_position_gpr;
+ alu.src[1].chan = 3;
+ alu.dst.sel = tmp;
+ alu.dst.chan = 0;
+ alu.dst.write = 1;
+ alu.last = 1;
+ if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_AND_INT;
+ alu.src[0].sel = tmp;
+ alu.src[1].sel = ctx.face_gpr;
+ alu.src[1].chan = 2;
+ alu.dst.sel = ctx.face_gpr;
+ alu.dst.chan = 2;
+ alu.dst.write = 1;
+ alu.last = 1;
+ if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
+ return r;
}
+
if (ctx.fragcoord_input >= 0) {
if (ctx.bc->chip_class == CAYMAN) {
for (j = 0 ; j < 4; j++) {
alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
alu.dst.chan = j;
alu.dst.write = (j == 3);
- alu.last = 1;
+ alu.last = (j == 3);
if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
return r;
}
ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
else
ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
+
+ ctx.bc->precise |= ctx.parse.FullToken.FullInstruction.Instruction.Precise;
+
r = ctx.inst_info->process(&ctx);
if (r)
goto out_err;
output[j].op = CF_OP_EXPORT;
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
shader->nr_ps_color_exports++;
+ if (k > shader->ps_export_highest)
+ shader->ps_export_highest = k;
shader->ps_color_export_mask |= (0xf << (j * 4));
}
}
return r;
}
+ free(ctx.spilled_arrays);
+ free(ctx.array_infos);
free(ctx.literals);
tgsi_parse_free(&ctx.parse);
return 0;
out_err:
+ free(ctx.spilled_arrays);
+ free(ctx.array_infos);
free(ctx.literals);
tgsi_parse_free(&ctx.parse);
return r;
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
- r600_dst->sel = tgsi_dst->Register.Index;
- r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
+ if (tgsi_dst->Register.File == TGSI_FILE_TEMPORARY) {
+ bool spilled;
+ unsigned idx;
+
+ idx = map_tgsi_reg_index_to_r600_gpr(ctx, tgsi_dst->Register.Index, &spilled);
+
+ if (spilled) {
+ struct r600_bytecode_output cf;
+ int reg = 0;
+ int r;
+ bool add_pending_output = true;
+
+ memset(&cf, 0, sizeof(struct r600_bytecode_output));
+ get_spilled_array_base_and_size(ctx, tgsi_dst->Register.Index,
+ &cf.array_base, &cf.array_size);
+
+ /* If no component has spilled, reserve a register and add the spill code
+ * ctx->bc->n_pending_outputs is cleared after each instruction group */
+ if (ctx->bc->n_pending_outputs == 0) {
+ reg = r600_get_temp(ctx);
+ } else {
+ /* If we are already spilling and the output address is the same like
+ * before then just reuse the same slot */
+ struct r600_bytecode_output *tmpl = &ctx->bc->pending_outputs[ctx->bc->n_pending_outputs-1];
+ if ((cf.array_base + idx == tmpl->array_base) ||
+ (cf.array_base == tmpl->array_base &&
+ tmpl->index_gpr == ctx->bc->ar_reg &&
+ tgsi_dst->Register.Indirect)) {
+ reg = ctx->bc->pending_outputs[0].gpr;
+ add_pending_output = false;
+ } else {
+ reg = r600_get_temp(ctx);
+ }
+ }
+
+ r600_dst->sel = reg;
+ r600_dst->chan = swizzle;
+ r600_dst->write = 1;
+ if (inst->Instruction.Saturate) {
+ r600_dst->clamp = 1;
+ }
+
+ /* Add new outputs as pending */
+ if (add_pending_output) {
+ cf.op = CF_OP_MEM_SCRATCH;
+ cf.elem_size = 3;
+ cf.gpr = reg;
+ cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
+ cf.mark = 1;
+ cf.comp_mask = inst->Dst[0].Register.WriteMask;
+ cf.swizzle_x = 0;
+ cf.swizzle_y = 1;
+ cf.swizzle_z = 2;
+ cf.swizzle_w = 3;
+ cf.burst_count = 1;
+
+ if (tgsi_dst->Register.Indirect) {
+ if (ctx->bc->chip_class < R700)
+ cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
+ else
+ cf.type = 3; // V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK;
+ cf.index_gpr = ctx->bc->ar_reg;
+ }
+ else {
+ cf.array_base += idx;
+ cf.array_size = 0;
+ }
+
+ r = r600_bytecode_add_pending_output(ctx->bc, &cf);
+ if (r)
+ return;
+
+ if (ctx->bc->chip_class >= R700)
+ r600_bytecode_need_wait_ack(ctx->bc, true);
+ }
+ return;
+ }
+ else {
+ r600_dst->sel = idx;
+ }
+ }
+ else {
+ r600_dst->sel = tgsi_dst->Register.Index;
+ r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
+ }
r600_dst->chan = swizzle;
r600_dst->write = 1;
if (inst->Instruction.Saturate) {
struct r600_bytecode_alu alu;
int i, r, j;
unsigned write_mask = inst->Dst[0].Register.WriteMask;
+ int lasti = tgsi_last_instruction(write_mask);
int tmp0 = ctx->temp_reg;
int tmp1 = r600_get_temp(ctx);
int tmp2 = r600_get_temp(ctx);
int tmp3 = r600_get_temp(ctx);
+ int tmp4 = 0;
+
+ /* Use additional temp if dst register and src register are the same */
+ if (inst->Src[0].Register.Index == inst->Dst[0].Register.Index ||
+ inst->Src[1].Register.Index == inst->Dst[0].Register.Index) {
+ tmp4 = r600_get_temp(ctx);
+ }
+
/* Unsigned path:
*
* we need to represent src1 as src2*q + r, where q - quotient, r - remainder
alu.dst.chan = 2;
alu.dst.write = 1;
} else {
- tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+ if (tmp4 > 0) {
+ alu.dst.sel = tmp4;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ } else {
+ tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+ }
}
alu.src[0].sel = tmp1;
alu.op = ALU_OP3_CNDGE_INT;
alu.is_op3 = 1;
- tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+ if (tmp4 > 0) {
+ alu.dst.sel = tmp4;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ } else {
+ tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+ }
r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
alu.src[1].sel = tmp0;
alu.op = ALU_OP3_CNDGE_INT;
alu.is_op3 = 1;
- tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+ if (tmp4 > 0) {
+ alu.dst.sel = tmp4;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ } else {
+ tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+ }
alu.src[0].sel = tmp2;
alu.src[0].chan = 2;
}
}
}
+
+ if (tmp4 > 0) {
+ for (i = 0; i <= lasti; ++i) {
+ if (!(write_mask & (1<<i)))
+ continue;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+ alu.src[0].sel = tmp4;
+ alu.src[0].chan = i;
+
+ if (i == lasti)
+ alu.last = 1;
+ if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
+ return r;
+ }
+ }
+
return 0;
}
static int tgsi_ssg(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ unsigned write_mask = inst->Dst[0].Register.WriteMask;
+ int last_inst = tgsi_last_instruction(write_mask);
struct r600_bytecode_alu alu;
int i, r;
/* tmp = (src > 0 ? 1 : src) */
- for (i = 0; i < 4; i++) {
+ for (i = 0; i <= last_inst; i++) {
+ if (!(write_mask & (1 << i)))
+ continue;
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP3_CNDGT;
alu.is_op3 = 1;
alu.src[1].sel = V_SQ_ALU_SRC_1;
r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
- if (i == 3)
+ if (i == last_inst)
alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, &alu);
if (r)
}
/* dst = (-tmp > 0 ? -1 : tmp) */
- for (i = 0; i < 4; i++) {
+ for (i = 0; i <= last_inst; i++) {
+ if (!(write_mask & (1 << i)))
+ continue;
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP3_CNDGT;
alu.is_op3 = 1;
alu.src[2].sel = ctx->temp_reg;
alu.src[2].chan = i;
- if (i == 3)
+ if (i == last_inst)
alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, &alu);
if (r)
}
else {
location = TGSI_INTERPOLATE_LOC_CENTROID;
+ ctx->shader->input[input].uses_interpolate_at_centroid = 1;
}
k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
}
static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
- unsigned temp, int chan,
+ unsigned writemask,
struct r600_bytecode_alu_src *bc_src,
const struct r600_shader_src *shader_src)
{
struct r600_bytecode_alu alu;
- int r;
+ int i, r;
+ int lasti = tgsi_last_instruction(writemask);
+ int temp_reg = 0;
- r600_bytecode_src(bc_src, shader_src, chan);
+ r600_bytecode_src(&bc_src[0], shader_src, 0);
+ r600_bytecode_src(&bc_src[1], shader_src, 1);
+ r600_bytecode_src(&bc_src[2], shader_src, 2);
+ r600_bytecode_src(&bc_src[3], shader_src, 3);
- /* op3 operands don't support abs modifier */
if (bc_src->abs) {
- assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP1_MOV;
- alu.dst.sel = temp;
- alu.dst.chan = chan;
- alu.dst.write = 1;
+ temp_reg = r600_get_temp(ctx);
- alu.src[0] = *bc_src;
- alu.last = true; // sufficient?
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
-
- memset(bc_src, 0, sizeof(*bc_src));
- bc_src->sel = temp;
- bc_src->chan = chan;
+ for (i = 0; i < lasti + 1; i++) {
+ if (!(writemask & (1 << i)))
+ continue;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.dst.sel = temp_reg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.src[0] = bc_src[i];
+ if (i == lasti) {
+ alu.last = 1;
+ }
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ memset(&bc_src[i], 0, sizeof(*bc_src));
+ bc_src[i].sel = temp_reg;
+ bc_src[i].chan = i;
+ }
}
return 0;
}
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
+ struct r600_bytecode_alu_src srcs[4][4];
int i, j, r;
int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
- int temp_regs[4];
unsigned op = ctx->inst_info->op;
if (op == ALU_OP3_MULADD_IEEE &&
op = ALU_OP3_MULADD;
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
- temp_regs[j] = 0;
- if (ctx->src[j].abs)
- temp_regs[j] = r600_get_temp(ctx);
+ r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
+ srcs[j], &ctx->src[j]);
+ if (r)
+ return r;
}
+
for (i = 0; i < lasti + 1; i++) {
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
continue;
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = op;
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
- r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
- if (r)
- return r;
+ alu.src[j] = srcs[j][i];
}
if (dst == -1) {
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
struct r600_bytecode_tex tex;
+ struct r600_bytecode_tex grad_offs[3];
struct r600_bytecode_alu alu;
unsigned src_gpr;
- int r, i, j;
+ int r, i, j, n_grad_offs = 0;
int opcode;
bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
int8_t offset_x = 0, offset_y = 0, offset_z = 0;
boolean has_txq_cube_array_z = false;
unsigned sampler_index_mode;
+ int array_index_offset_channel = -1;
if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
if (r)
return r;
+ /* Evaluate the array index according to floor(idx + 0.5). This
+ * needs to be done before merging the face select value, because
+ * otherwise the fractional part of the array index will interfere
+ * with the face select value */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
+ alu.op = ALU_OP1_RNDNE;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = 3;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* Because the array slice index and the cube face index are merged
+ * into one value we have to make sure the array slice index is >= 0,
+ * otherwise the face selection will fail */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MAX;
+ alu.src[0].sel = ctx->temp_reg;
+ alu.src[0].chan = 3;
+ alu.src[1].sel = V_SQ_ALU_SRC_0;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = 3;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
/* have to multiply original layer by 8 and add to face id (temp.w) in Z */
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP3_MULADD;
alu.is_op3 = 1;
- r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
+ alu.src[0].sel = ctx->temp_reg;
+ alu.src[0].chan = 3;
alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
alu.src[1].chan = 0;
alu.src[1].value = u_bitcast_f2u(8.0f);
}
for (i = 1; i < 3; i++) {
/* set gradients h/v */
- memset(&tex, 0, sizeof(struct r600_bytecode_tex));
- tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
+ struct r600_bytecode_tex *t = &grad_offs[n_grad_offs++];
+ memset(t, 0, sizeof(struct r600_bytecode_tex));
+ t->op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
FETCH_OP_SET_GRADIENTS_V;
- tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
- tex.sampler_index_mode = sampler_index_mode;
- tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
- tex.resource_index_mode = sampler_index_mode;
-
- tex.src_gpr = (i == 1) ? temp_h : temp_v;
- tex.src_sel_x = 0;
- tex.src_sel_y = 1;
- tex.src_sel_z = 2;
- tex.src_sel_w = 3;
-
- tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
- tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
+ t->sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
+ t->sampler_index_mode = sampler_index_mode;
+ t->resource_id = t->sampler_id + R600_MAX_CONST_BUFFERS;
+ t->resource_index_mode = sampler_index_mode;
+
+ t->src_gpr = (i == 1) ? temp_h : temp_v;
+ t->src_sel_x = 0;
+ t->src_sel_y = 1;
+ t->src_sel_z = 2;
+ t->src_sel_w = 3;
+
+ t->dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
+ t->dst_sel_x = t->dst_sel_y = t->dst_sel_z = t->dst_sel_w = 7;
if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
- tex.coord_type_x = 1;
- tex.coord_type_y = 1;
- tex.coord_type_z = 1;
- tex.coord_type_w = 1;
+ t->coord_type_x = 1;
+ t->coord_type_y = 1;
+ t->coord_type_z = 1;
+ t->coord_type_w = 1;
}
- r = r600_bytecode_add_tex(ctx->bc, &tex);
- if (r)
- return r;
+ }
+ }
+
+ if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
+ /* Gather4 should follow the same rules as bilinear filtering, but the hardware
+ * incorrectly forces nearest filtering if the texture format is integer.
+ * The only effect it has on Gather4, which always returns 4 texels for
+ * bilinear filtering, is that the final coordinates are off by 0.5 of
+ * the texel size.
+ *
+ * The workaround is to subtract 0.5 from the unnormalized coordinates,
+ * or (0.5 / size) from the normalized coordinates.
+ */
+ if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
+ inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
+ int treg = r600_get_temp(ctx);
+
+ /* mov array and comparison oordinate to temp_reg if needed */
+ if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
+ inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
+ inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) && !src_loaded) {
+ int end = inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ? 3 : 2;
+ for (i = 2; i <= end; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.last = (i == end);
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+
+ if (inst->Texture.Texture == TGSI_TEXTURE_RECT ||
+ inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_ADD;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.last = i == 1;
+ if (src_loaded) {
+ alu.src[0].sel = ctx->temp_reg;
+ alu.src[0].chan = i;
+ } else
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
+ alu.src[1].sel = V_SQ_ALU_SRC_0_5;
+ alu.src[1].neg = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ } else {
+ /* execute a TXQ */
+ memset(&tex, 0, sizeof(struct r600_bytecode_tex));
+ tex.op = FETCH_OP_GET_TEXTURE_RESINFO;
+ tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
+ tex.sampler_index_mode = sampler_index_mode;
+ tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
+ tex.resource_index_mode = sampler_index_mode;
+ tex.dst_gpr = treg;
+ tex.src_sel_x = 4;
+ tex.src_sel_y = 4;
+ tex.src_sel_z = 4;
+ tex.src_sel_w = 4;
+ tex.dst_sel_x = 0;
+ tex.dst_sel_y = 1;
+ tex.dst_sel_z = 7;
+ tex.dst_sel_w = 7;
+ r = r600_bytecode_add_tex(ctx->bc, &tex);
+ if (r)
+ return r;
+
+ /* coord.xy = -0.5 * (1.0/int_to_flt(size)) + coord.xy */
+ if (ctx->bc->chip_class == CAYMAN) {
+ /* */
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_INT_TO_FLT;
+ alu.dst.sel = treg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = i;
+ alu.last = (i == 1) ? 1 : 0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ for (j = 0; j < 2; j++) {
+ for (i = 0; i < 3; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_RECIP_IEEE;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = j;
+ alu.dst.sel = treg;
+ alu.dst.chan = i;
+ if (i == 2)
+ alu.last = 1;
+ if (i == j)
+ alu.dst.write = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+ } else {
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_INT_TO_FLT;
+ alu.dst.sel = treg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = i;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_RECIP_IEEE;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = i;
+ alu.dst.sel = treg;
+ alu.dst.chan = i;
+ alu.last = 1;
+ alu.dst.write = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP3_MULADD;
+ alu.is_op3 = 1;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.last = i == 1;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = i;
+ alu.src[1].sel = V_SQ_ALU_SRC_0_5;
+ alu.src[1].neg = 1;
+ if (src_loaded) {
+ alu.src[2].sel = ctx->temp_reg;
+ alu.src[2].chan = i;
+ } else
+ r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+ src_loaded = TRUE;
+ src_gpr = ctx->temp_reg;
}
}
if (opcode == FETCH_OP_GATHER4 &&
inst->TexOffsets[0].File != TGSI_FILE_NULL &&
inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
+ struct r600_bytecode_tex *t;
opcode = FETCH_OP_GATHER4_O;
/* GATHER4_O/GATHER4_C_O use offset values loaded by
SET_TEXTURE_OFFSETS instruction. The immediate offset values
encoded in the instruction are ignored. */
- memset(&tex, 0, sizeof(struct r600_bytecode_tex));
- tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
- tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
- tex.sampler_index_mode = sampler_index_mode;
- tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
- tex.resource_index_mode = sampler_index_mode;
+ t = &grad_offs[n_grad_offs++];
+ memset(t, 0, sizeof(struct r600_bytecode_tex));
+ t->op = FETCH_OP_SET_TEXTURE_OFFSETS;
+ t->sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
+ t->sampler_index_mode = sampler_index_mode;
+ t->resource_id = t->sampler_id + R600_MAX_CONST_BUFFERS;
+ t->resource_index_mode = sampler_index_mode;
+
+ t->src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
+ t->src_sel_x = inst->TexOffsets[0].SwizzleX;
+ t->src_sel_y = inst->TexOffsets[0].SwizzleY;
+ if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
+ inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)
+ /* make sure array index selector is 0, this is just a safety
+ * precausion because TGSI seems to emit something strange here */
+ t->src_sel_z = 4;
+ else
+ t->src_sel_z = inst->TexOffsets[0].SwizzleZ;
- tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
- tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
- tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
- tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
- tex.src_sel_w = 4;
+ t->src_sel_w = 4;
- tex.dst_sel_x = 7;
- tex.dst_sel_y = 7;
- tex.dst_sel_z = 7;
- tex.dst_sel_w = 7;
-
- r = r600_bytecode_add_tex(ctx->bc, &tex);
- if (r)
- return r;
+ t->dst_sel_x = 7;
+ t->dst_sel_y = 7;
+ t->dst_sel_z = 7;
+ t->dst_sel_w = 7;
}
if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
tex.inst_mod = texture_component_select;
if (ctx->bc->chip_class == CAYMAN) {
- /* GATHER4 result order is different from TGSI TG4 */
- tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
- tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
- tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
+ tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+ tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
+ tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
} else {
- tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
- tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
- tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+ /* GATHER4 result order is different from TGSI TG4 */
+ tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 1 : 7;
+ tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 2 : 7;
+ tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 0 : 7;
tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
}
}
opcode == FETCH_OP_SAMPLE_C_LB) {
/* the array index is read from Y */
tex.coord_type_y = 0;
+ array_index_offset_channel = tex.src_sel_y;
} else {
/* the array index is read from Z */
tex.coord_type_z = 0;
tex.src_sel_z = tex.src_sel_y;
+ array_index_offset_channel = tex.src_sel_z;
}
} else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
- inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
- ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
+ inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) {
+ tex.coord_type_z = 0;
+ array_index_offset_channel = tex.src_sel_z;
+ } else if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
- (ctx->bc->chip_class >= EVERGREEN)))
- /* the array index is read from Z */
+ (ctx->bc->chip_class >= EVERGREEN))
+ /* the array index is read from Z, coordinate will be corrected elsewhere */
tex.coord_type_z = 0;
+ /* We have array access to 1D or 2D ARRAY, the coordinates are not int ->
+ * evaluate the array index */
+ if (array_index_offset_channel >= 0 &&
+ opcode != FETCH_OP_LD &&
+ opcode != FETCH_OP_GET_TEXTURE_RESINFO) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.src[0].sel = tex.src_gpr;
+ alu.src[0].chan = array_index_offset_channel;
+ alu.src[0].rel = tex.src_rel;
+ alu.op = ALU_OP1_RNDNE;
+ alu.dst.sel = tex.src_gpr;
+ alu.dst.chan = array_index_offset_channel;
+ alu.dst.rel = tex.src_rel;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+
/* mask unused source components */
if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
switch (inst->Texture.Texture) {
}
}
+ /* Emit set gradient and offset instructions. */
+ for (i = 0; i < n_grad_offs; ++i) {
+ r = r600_bytecode_add_tex(ctx->bc, &grad_offs[i]);
+ if (r)
+ return r;
+ }
+
r = r600_bytecode_add_tex(ctx->bc, &tex);
if (r)
return r;
unsigned rat_index_mode;
unsigned immed_base;
- r = load_thread_id_gpr(ctx);
- if (r)
- return r;
-
rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
rat_base = ctx->shader->rat_base;
- r = load_thread_id_gpr(ctx);
- if (r)
- return r;
-
if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
- unsigned i, temp_regs[2];
+ struct r600_bytecode_alu_src srcs[2][4];
+ unsigned i;
int r;
/* optimize if it's just an equal balance */
}
/* src0 * src1 + (1 - src0) * src2 */
- if (ctx->src[0].abs)
- temp_regs[0] = r600_get_temp(ctx);
- else
- temp_regs[0] = 0;
- if (ctx->src[1].abs)
- temp_regs[1] = r600_get_temp(ctx);
- else
- temp_regs[1] = 0;
+
+ for (i = 0; i < 2; i++) {
+ r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
+ srcs[i], &ctx->src[i]);
+ if (r)
+ return r;
+ }
for (i = 0; i < lasti + 1; i++) {
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP3_MULADD;
alu.is_op3 = 1;
- r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
- if (r)
- return r;
- r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
- if (r)
- return r;
+ alu.src[0] = srcs[0][i];
+ alu.src[1] = srcs[1][i];
alu.src[2].sel = ctx->temp_reg;
alu.src[2].chan = i;
struct r600_bytecode_alu alu;
int i, r, j;
int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
- int temp_regs[3];
+ struct r600_bytecode_alu_src srcs[3][4];
+
unsigned op;
if (ctx->src[0].abs && ctx->src[0].neg) {
}
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
- temp_regs[j] = 0;
- if (ctx->src[j].abs)
- temp_regs[j] = r600_get_temp(ctx);
+ r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
+ srcs[j], &ctx->src[j]);
+ if (r)
+ return r;
}
for (i = 0; i < lasti + 1; i++) {
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = op;
- r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
- if (r)
- return r;
- r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
- if (r)
- return r;
- r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
- if (r)
- return r;
+ alu.src[0] = srcs[0][i];
+ alu.src[1] = srcs[2][i];
+ alu.src[2] = srcs[1][i];
+
tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
alu.dst.chan = i;
alu.dst.write = 1;
return 0;
}
-static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
+static inline int callstack_update_max_depth(struct r600_shader_ctx *ctx,
unsigned reason)
{
struct r600_stack_info *stack = &ctx->bc->stack;
/* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
* the stack must be reserved to hold the current active/continue
* masks */
- if (reason == FC_PUSH_VPM) {
+ if (reason == FC_PUSH_VPM || stack->push > 0) {
elements += 2;
}
break;
* NOTE: it seems we also need to reserve additional element in some
* other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
* then STACK_SIZE should be 2 instead of 1 */
- if (reason == FC_PUSH_VPM) {
+ if (reason == FC_PUSH_VPM || stack->push > 0) {
elements += 1;
}
break;
if (entries > stack->max_entries)
stack->max_entries = entries;
+ return elements;
}
static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
}
}
-static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
+static inline int callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
{
switch (reason) {
case FC_PUSH_VPM:
break;
case FC_PUSH_WQM:
++ctx->bc->stack.push_wqm;
+ break;
case FC_LOOP:
++ctx->bc->stack.loop;
break;
assert(0);
}
- callstack_update_max_depth(ctx, reason);
+ return callstack_update_max_depth(ctx, reason);
}
static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
struct r600_bytecode_alu_src *src)
{
int alu_type = CF_OP_ALU_PUSH_BEFORE;
+ bool needs_workaround = false;
+ int elems = callstack_push(ctx, FC_PUSH_VPM);
+
+ if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1)
+ needs_workaround = true;
+
+ if (ctx->bc->chip_class == EVERGREEN && ctx_needs_stack_workaround_8xx(ctx)) {
+ unsigned dmod1 = (elems - 1) % ctx->bc->stack.entry_size;
+ unsigned dmod2 = (elems) % ctx->bc->stack.entry_size;
+
+ if (elems && (!dmod1 || !dmod2))
+ needs_workaround = true;
+ }
/* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
* LOOP_STARTxxx for nested loops may put the branch stack into a state
* such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
* by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
- if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
+ if (needs_workaround) {
r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
alu_type = CF_OP_ALU;
fc_pushlevel(ctx, FC_IF);
- callstack_push(ctx, FC_PUSH_VPM);
return 0;
}
static int tgsi_endif(struct r600_shader_ctx *ctx)
{
+ int offset = 2;
pops(ctx, 1);
if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
R600_ERR("if/endif unbalanced in shader\n");
return -1;
}
+ /* ALU_EXTENDED needs 4 DWords instead of two, adjust jump target offset accordingly */
+ if (ctx->bc->cf_last->eg_alu_extended)
+ offset += 2;
+
if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
- ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
+ ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + offset;
ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
} else {
- ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
+ ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + offset;
}
fc_poplevel(ctx);
alu.op = ALU_OP1_MOV;
tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
+ alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, &alu);
if (r)
return r;
projects / mesa.git / blobdiff