{
struct radeon_cmdbuf *cs = ctx->dma_cs;
unsigned i, ncopy, csize;
- struct si_resource *rdst = si_resource(dst);
- struct si_resource *rsrc = si_resource(src);
+ struct si_resource *sdst = si_resource(dst);
+ struct si_resource *ssrc = si_resource(src);
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
* that range. */
- util_range_add(&rdst->valid_buffer_range, dst_offset,
+ util_range_add(&sdst->valid_buffer_range, dst_offset,
dst_offset + size);
- dst_offset += rdst->gpu_address;
- src_offset += rsrc->gpu_address;
+ dst_offset += sdst->gpu_address;
+ src_offset += ssrc->gpu_address;
ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
- si_need_dma_space(ctx, ncopy * 7, rdst, rsrc);
+ si_need_dma_space(ctx, ncopy * 7, sdst, ssrc);
for (i = 0; i < ncopy; i++) {
csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);