radeonsi: stop using TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS

[mesa.git] / src / gallium / drivers / radeonsi / si_buffer.c

diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c
index eb71636d3462477bcbf9a928e5b80ca5187fd8fd..e64b51d8d0aceb4fb1179ea4dbe9bfd4ac3e4ae7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -166,6 +166,13 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
    else
       res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 
+   if (sscreen->ws->ws_is_secure(sscreen->ws)) {
+      if (res->b.b.bind & PIPE_BIND_SCANOUT)
+         res->flags |= RADEON_FLAG_ENCRYPTED;
+      if (res->b.b.flags & PIPE_RESOURCE_FLAG_ENCRYPTED)
+         res->flags |= RADEON_FLAG_ENCRYPTED;
+   }
+
    if (sscreen->debug_flags & DBG(NO_WC))
       res->flags &= ~RADEON_FLAG_GTT_WC;
 
@@ -175,6 +182,14 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
    if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
       res->flags |= RADEON_FLAG_32BIT;
 
+   /* For higher throughput and lower latency over PCIe assuming sequential access.
+    * Only CP DMA, SDMA, and optimized compute benefit from this.
+    * GFX8 and older don't support RADEON_FLAG_UNCACHED.
+    */
+   if (sscreen->info.chip_class >= GFX9 &&
+       res->b.b.flags & SI_RESOURCE_FLAG_UNCACHED)
+      res->flags |= RADEON_FLAG_UNCACHED;
+
    /* Set expected VRAM and GART usage for the buffer. */
    res->vram_usage = 0;
    res->gart_usage = 0;
@@ -324,7 +339,9 @@ static void *si_buffer_get_transfer(struct pipe_context *ctx, struct pipe_resour
    struct si_context *sctx = (struct si_context *)ctx;
    struct si_transfer *transfer;
 
-   if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
+   if (usage & PIPE_TRANSFER_THREAD_SAFE)
+      transfer = malloc(sizeof(*transfer));
+   else if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
       transfer = slab_alloc(&sctx->pool_transfers_unsync);
    else
       transfer = slab_alloc(&sctx->pool_transfers);
@@ -461,9 +478,10 @@ static void *si_buffer_transfer_map(struct pipe_context *ctx, struct pipe_resour
             (buf->flags & RADEON_FLAG_SPARSE)) {
       struct si_resource *staging;
 
-      assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
-      staging = si_resource(pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_STAGING,
-                                               box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT)));
+      assert(!(usage & (TC_TRANSFER_MAP_THREADED_UNSYNC | PIPE_TRANSFER_THREAD_SAFE)));
+      staging = si_aligned_buffer_create(ctx->screen, SI_RESOURCE_FLAG_UNCACHED,
+                                         PIPE_USAGE_STAGING,
+                                         box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT), 256);
       if (staging) {
          /* Copy the VRAM buffer to the staging buffer. */
          si_sdma_copy_buffer(sctx, &staging->b.b, resource, box->x % SI_MAP_BUFFER_ALIGNMENT,
@@ -574,9 +592,14 @@ static void si_buffer_transfer_unmap(struct pipe_context *ctx, struct pipe_trans
    assert(stransfer->b.staging == NULL); /* for threaded context only */
    pipe_resource_reference(&transfer->resource, NULL);
 
-   /* Don't use pool_transfers_unsync. We are always in the driver
-    * thread. */
-   slab_free(&sctx->pool_transfers, transfer);
+   if (transfer->usage & PIPE_TRANSFER_THREAD_SAFE) {
+      free(transfer);
+   } else {
+      /* Don't use pool_transfers_unsync. We are always in the driver
+       * thread. Freeing an object into a different pool is allowed.
+       */
+      slab_free(&sctx->pool_transfers, transfer);
+   }
 }
 
 static void si_buffer_subdata(struct pipe_context *ctx, struct pipe_resource *buffer,