radeonsi: remove redundant si_shader_info::images_declared
[mesa.git] / src / gallium / drivers / radeonsi / si_debug.c
index f596d51e0f6b805a8ae9006504fde4ba903ee155..8fc7e4e088e18f3aaa438d91de4c34f5ace63d70 100644 (file)
@@ -777,9 +777,10 @@ static unsigned si_identity(unsigned slot)
    return slot;
 }
 
-static void si_dump_descriptors(struct si_context *sctx, enum pipe_shader_type processor,
+static void si_dump_descriptors(struct si_context *sctx, gl_shader_stage stage,
                                 const struct si_shader_info *info, struct u_log_context *log)
 {
+   enum pipe_shader_type processor = pipe_shader_type_from_mesa(stage);
    struct si_descriptors *descs =
       &sctx->descriptors[SI_DESCS_FIRST_SHADER + processor * SI_NUM_SHADER_DESCS];
    static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
@@ -789,20 +790,25 @@ static void si_dump_descriptors(struct si_context *sctx, enum pipe_shader_type p
 
    if (info) {
       enabled_constbuf = info->const_buffers_declared;
-      enabled_shaderbuf = info->shader_buffers_declared;
-      enabled_samplers = info->samplers_declared;
-      enabled_images = info->images_declared;
+      enabled_shaderbuf = u_bit_consecutive(0, info->base.num_ssbos);
+      enabled_samplers = info->base.textures_used;
+      enabled_images = u_bit_consecutive(0, info->base.num_images);
    } else {
       enabled_constbuf =
          sctx->const_and_shader_buffers[processor].enabled_mask >> SI_NUM_SHADER_BUFFERS;
       enabled_shaderbuf = sctx->const_and_shader_buffers[processor].enabled_mask &
-                          u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
-      enabled_shaderbuf = util_bitreverse(enabled_shaderbuf) >> (32 - SI_NUM_SHADER_BUFFERS);
+                          u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS);
+      enabled_shaderbuf = 0;
+      for (int i = 0; i < SI_NUM_SHADER_BUFFERS; i++) {
+         enabled_shaderbuf |=
+            (sctx->const_and_shader_buffers[processor].enabled_mask &
+             1llu << (SI_NUM_SHADER_BUFFERS - i - 1)) << i;
+      }
       enabled_samplers = sctx->samplers[processor].enabled_mask;
       enabled_images = sctx->images[processor].enabled_mask;
    }
 
-   if (processor == PIPE_SHADER_VERTEX && sctx->vb_descriptors_buffer &&
+   if (stage == MESA_SHADER_VERTEX && sctx->vb_descriptors_buffer &&
        sctx->vb_descriptors_gpu_list && sctx->vertex_elements) {
       assert(info); /* only CS may not have an info struct */
       struct si_descriptors desc = {};
@@ -837,7 +843,7 @@ static void si_dump_gfx_descriptors(struct si_context *sctx,
    if (!state->cso || !state->current)
       return;
 
-   si_dump_descriptors(sctx, state->cso->type, &state->cso->info, log);
+   si_dump_descriptors(sctx, state->cso->info.stage, &state->cso->info, log);
 }
 
 static void si_dump_compute_descriptors(struct si_context *sctx, struct u_log_context *log)
@@ -845,7 +851,7 @@ static void si_dump_compute_descriptors(struct si_context *sctx, struct u_log_co
    if (!sctx->cs_shader_state.program)
       return;
 
-   si_dump_descriptors(sctx, PIPE_SHADER_COMPUTE, NULL, log);
+   si_dump_descriptors(sctx, MESA_SHADER_COMPUTE, NULL, log);
 }
 
 struct si_shader_inst {
@@ -868,11 +874,11 @@ struct si_shader_inst {
 static void si_add_split_disasm(struct si_screen *screen, struct ac_rtld_binary *rtld_binary,
                                 struct si_shader_binary *binary, uint64_t *addr, unsigned *num,
                                 struct si_shader_inst *instructions,
-                                enum pipe_shader_type shader_type, unsigned wave_size)
+                                gl_shader_stage stage, unsigned wave_size)
 {
    if (!ac_rtld_open(rtld_binary, (struct ac_rtld_open_info){
                                      .info = &screen->info,
-                                     .shader_type = tgsi_processor_to_shader_stage(shader_type),
+                                     .shader_type = stage,
                                      .wave_size = wave_size,
                                      .num_parts = 1,
                                      .elf_ptrs = &binary->elf_buffer,
@@ -920,7 +926,7 @@ static void si_print_annotated_shader(struct si_shader *shader, struct ac_wave_i
       return;
 
    struct si_screen *screen = shader->selector->screen;
-   enum pipe_shader_type shader_type = shader->selector->type;
+   gl_shader_stage stage = shader->selector->info.stage;
    uint64_t start_addr = shader->bo->gpu_address;
    uint64_t end_addr = start_addr + shader->bo->b.b.width0;
    unsigned i;
@@ -949,21 +955,21 @@ static void si_print_annotated_shader(struct si_shader *shader, struct ac_wave_i
 
    if (shader->prolog) {
       si_add_split_disasm(screen, &rtld_binaries[0], &shader->prolog->binary, &inst_addr, &num_inst,
-                          instructions, shader_type, wave_size);
+                          instructions, stage, wave_size);
    }
    if (shader->previous_stage) {
       si_add_split_disasm(screen, &rtld_binaries[1], &shader->previous_stage->binary, &inst_addr,
-                          &num_inst, instructions, shader_type, wave_size);
+                          &num_inst, instructions, stage, wave_size);
    }
    if (shader->prolog2) {
       si_add_split_disasm(screen, &rtld_binaries[2], &shader->prolog2->binary, &inst_addr,
-                          &num_inst, instructions, shader_type, wave_size);
+                          &num_inst, instructions, stage, wave_size);
    }
    si_add_split_disasm(screen, &rtld_binaries[3], &shader->binary, &inst_addr, &num_inst,
-                       instructions, shader_type, wave_size);
+                       instructions, stage, wave_size);
    if (shader->epilog) {
       si_add_split_disasm(screen, &rtld_binaries[4], &shader->epilog->binary, &inst_addr, &num_inst,
-                          instructions, shader_type, wave_size);
+                          instructions, stage, wave_size);
    }
 
    fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",