#include "si_pipe.h"
#include "si_compute.h"
+#include "si_build_pm4.h"
#include "sid.h"
#include "util/format/u_format.h"
#include "util/hash_table.h"
state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch);
} else {
+ uint16_t epitch = tex->surface.u.gfx9.surf.epitch;
+ if (tex->buffer.b.b.format == PIPE_FORMAT_R8G8_R8B8_UNORM &&
+ block_width == 1) {
+ /* epitch is patched in ac_surface for sdma/vcn blocks to get
+ * a value expressed in elements unit.
+ * But here the texture is used with block_width == 1 so we
+ * need epitch in pixel units.
+ */
+ epitch = (epitch + 1) / tex->surface.blk_w - 1;
+ }
state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
- state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.surf.epitch);
+ state[4] |= S_008F20_PITCH(epitch);
}
state[5] &=
static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset,
unsigned pointer_count)
{
+ SI_CHECK_SHADOWED_REGS(sh_offset, pointer_count);
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count, 0));
radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
}
si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
return;
+ } else if (sctx->chip_class == GFX9 && sctx->shadowed_regs) {
+ /* We can't use the COMMON registers with register shadowing. */
+ si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
+ si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
+ si_emit_shader_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
+ si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_LS_0);
+ return;
} else if (sctx->chip_class == GFX9) {
/* Broadcast it to all shader stages. */
si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
unsigned num_sgprs = 8;
/* Image buffers are in desc[4..7]. */
- if (shader->info.image_buffers & (1 << i)) {
+ if (shader->info.base.image_buffers & (1 << i)) {
desc_offset += 4;
num_sgprs = 4;
}
si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[i]);
use_encrypted_bo |=
si_sampler_views_check_encrypted(sctx, &sctx->samplers[i],
- current_shader[i]->cso->info.samplers_declared);
+ current_shader[i]->cso->info.base.textures_used);
use_encrypted_bo |= si_image_views_check_encrypted(sctx, &sctx->images[i],
- current_shader[i]->cso->info.images_declared);
+ u_bit_consecutive(0, current_shader[i]->cso->info.base.num_images));
}
use_encrypted_bo |= si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
* or all writable buffers are encrypted.
*/
return si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[sh]) ||
- si_sampler_views_check_encrypted(sctx, &sctx->samplers[sh], info->samplers_declared) ||
- si_image_views_check_encrypted(sctx, &sctx->images[sh], info->images_declared) ||
+ si_sampler_views_check_encrypted(sctx, &sctx->samplers[sh], info->base.textures_used) ||
+ si_image_views_check_encrypted(sctx, &sctx->images[sh], u_bit_consecutive(0, info->base.num_images)) ||
si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
}
if (!sel)
return;
- si_set_active_descriptors(sctx, si_const_and_shader_buffer_descriptors_idx(sel->type),
+ si_set_active_descriptors(sctx, sel->const_and_shader_buf_descriptors_index,
sel->active_const_and_shader_buffers);
- si_set_active_descriptors(sctx, si_sampler_and_image_descriptors_idx(sel->type),
+ si_set_active_descriptors(sctx, sel->sampler_and_images_descriptors_index,
sel->active_samplers_and_images);
}