#include "si_pipe.h"
#include "si_compute.h"
+#include "si_build_pm4.h"
#include "sid.h"
#include "util/format/u_format.h"
#include "util/hash_table.h"
static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset,
unsigned pointer_count)
{
+ SI_CHECK_SHADOWED_REGS(sh_offset, pointer_count);
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count, 0));
radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
}
si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
return;
+ } else if (sctx->chip_class == GFX9 && sctx->shadowed_regs) {
+ /* We can't use the COMMON registers with register shadowing. */
+ si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
+ si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
+ si_emit_shader_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
+ si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_LS_0);
+ return;
} else if (sctx->chip_class == GFX9) {
/* Broadcast it to all shader stages. */
si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
if (!sel)
return;
- si_set_active_descriptors(sctx, si_const_and_shader_buffer_descriptors_idx(sel->type),
+ si_set_active_descriptors(sctx, sel->const_and_shader_buf_descriptors_index,
sel->active_const_and_shader_buffers);
- si_set_active_descriptors(sctx, si_sampler_and_image_descriptors_idx(sel->type),
+ si_set_active_descriptors(sctx, sel->sampler_and_images_descriptors_index,
sel->active_samplers_and_images);
}