nir: Add lower_rotate flag and set to true in all drivers

[mesa.git] / src / gallium / drivers / radeonsi / si_get.c

diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 67fbc50998b6008a5eb71ea28bdecf90a995b93c..dae5a55a3daa04577f26f414d9a18b96d022d8fe 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -48,13 +48,6 @@ static const char *si_get_device_vendor(struct pipe_screen *pscreen)
        return "AMD";
 }
 
-static const char *si_get_marketing_name(struct radeon_winsys *ws)
-{
-       if (!ws->get_chip_name)
-               return NULL;
-       return ws->get_chip_name(ws);
-}
-
 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 {
        struct si_screen *sscreen = (struct si_screen *)pscreen;
@@ -159,17 +152,18 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
        case PIPE_CAP_TGSI_BALLOT:
        case PIPE_CAP_TGSI_VOTE:
-       case PIPE_CAP_TGSI_FS_FBFETCH:
+       case PIPE_CAP_FBFETCH:
        case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
        case PIPE_CAP_IMAGE_LOAD_FORMATTED:
+       case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA:
+        case PIPE_CAP_TGSI_DIV:
                return 1;
 
        case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
                return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 
        case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
-               return sscreen->info.has_gpu_reset_status_query ||
-                      sscreen->info.has_gpu_reset_counter_query;
+               return sscreen->info.has_gpu_reset_status_query;
 
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
                return sscreen->info.has_2d_tiling;
@@ -203,14 +197,14 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
        case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
        case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
-               return !sscreen->info.has_unaligned_shader_loads;
+               return HAVE_LLVM < 0x0900 && !sscreen->info.has_unaligned_shader_loads;
 
        case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
                return sscreen->info.has_sparse_vm_mappings ?
                                RADEON_SPARSE_PAGE_SIZE : 0;
 
        case PIPE_CAP_PACKED_UNIFORMS:
-               if (sscreen->debug_flags & DBG(NIR))
+               if (sscreen->options.enable_nir)
                        return 1;
                return 0;
 
@@ -260,7 +254,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                return 32;
 
        case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
-               return sscreen->info.chip_class <= VI ?
+               return sscreen->info.chip_class <= GFX8 ?
                        PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 
        /* Stream output. */
@@ -270,7 +264,10 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 
        /* Geometry shader output. */
        case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
-               return 1024;
+               /* gfx9 has to report 256 to make piglit/gs-max-output pass.
+                * gfx8 and earlier can do 1024.
+                */
+               return 256;
        case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
                return 4095;
        case PIPE_CAP_MAX_GS_INVOCATIONS:
@@ -282,7 +279,8 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                return 2048;
 
        /* Texturing. */
-       case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+       case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
+               return 16384;
        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
                return 15; /* 16384 */
        case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
@@ -425,11 +423,11 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
        case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
                return SI_NUM_IMAGES;
        case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
-               if (sscreen->debug_flags & DBG(NIR))
+               if (sscreen->options.enable_nir)
                        return 0;
                return 32;
        case PIPE_SHADER_CAP_PREFERRED_IR:
-               if (sscreen->debug_flags & DBG(NIR))
+               if (sscreen->options.enable_nir)
                        return PIPE_SHADER_IR_NIR;
                return PIPE_SHADER_IR_TGSI;
        case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
@@ -490,8 +488,11 @@ static const struct nir_shader_compiler_options nir_options = {
        .lower_flrp64 = true,
        .lower_fsat = true,
        .lower_fdiv = true,
+       .lower_bitfield_insert_to_bitfield_select = true,
+       .lower_bitfield_extract = true,
        .lower_sub = true,
        .lower_ffma = true,
+       .lower_fmod = true,
        .lower_pack_snorm_2x16 = true,
        .lower_pack_snorm_4x8 = true,
        .lower_pack_unorm_2x16 = true,
@@ -502,9 +503,9 @@ static const struct nir_shader_compiler_options nir_options = {
        .lower_unpack_unorm_4x8 = true,
        .lower_extract_byte = true,
        .lower_extract_word = true,
+       .lower_rotate = true,
        .optimize_sample_mask_in = true,
        .max_unroll_iterations = 32,
-       .native_integers = true,
 };
 
 static const void *
@@ -634,7 +635,7 @@ static int si_get_video_param(struct pipe_screen *screen,
                                return true;
                        if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
                                return false;
-                       if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
+                       if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
                                RVID_ERR("No MJPEG support for the kernel version\n");
                                return false;
                        }
@@ -926,7 +927,7 @@ static void si_query_memory_info(struct pipe_screen *screen,
        info->device_memory_evicted =
                ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 
-       if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
+       if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
                info->nr_device_memory_evictions =
                        ws->query_value(ws, RADEON_NUM_EVICTIONS);
        else
@@ -943,14 +944,12 @@ static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 
 static void si_init_renderer_string(struct si_screen *sscreen)
 {
-       struct radeon_winsys *ws = sscreen->ws;
        char first_name[256], second_name[32] = {}, kernel_version[128] = {};
        struct utsname uname_data;
 
-       const char *marketing_name = si_get_marketing_name(ws);
-
-       if (marketing_name) {
-               snprintf(first_name, sizeof(first_name), "%s", marketing_name);
+       if (sscreen->info.marketing_name) {
+               snprintf(first_name, sizeof(first_name), "%s",
+                        sscreen->info.marketing_name);
                snprintf(second_name, sizeof(second_name), "%s, ",
                         sscreen->info.name);
        } else {