/* Max counters per HW block */
#define SI_QUERY_MAX_COUNTERS 16
-#define SI_PC_SHADERS_WINDOWING (1 << 31)
+#define SI_PC_SHADERS_WINDOWING (1u << 31)
struct si_query_group {
struct si_query_group *next;
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
- radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
- RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
-
- radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
- radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
- COPY_DATA_DST_SEL(COPY_DATA_DST_MEM_GRBM));
- radeon_emit(cs, 1); /* immediate */
- radeon_emit(cs, 0); /* unused */
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
+ si_cp_copy_data(sctx, sctx->gfx_cs,
+ COPY_DATA_DST_MEM, buffer, va - buffer->gpu_address,
+ COPY_DATA_IMM, NULL, 1);
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_DISABLE_AND_RESET));
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
- si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
+ si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
EOP_DATA_SEL_VALUE_32BIT,
buffer, va, 0, SI_NOT_QUERY);
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) |
- COPY_DATA_DST_SEL(COPY_DATA_DST_MEM_GRBM) |
+ COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
COPY_DATA_COUNT_SEL); /* 64 bits */
radeon_emit(cs, reg >> 2);
radeon_emit(cs, 0); /* unused */
for (idx = 0; idx < count; ++idx) {
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
- COPY_DATA_DST_SEL(COPY_DATA_DST_MEM_GRBM) |
+ COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
COPY_DATA_COUNT_SEL);
radeon_emit(cs, 0); /* immediate */
radeon_emit(cs, 0);
}
}
-static void si_pc_query_destroy(struct si_screen *sscreen,
+static void si_pc_query_destroy(struct si_context *sctx,
struct si_query *squery)
{
struct si_query_pc *query = (struct si_query_pc *)squery;
FREE(query->counters);
- si_query_buffer_destroy(sscreen, &query->buffer);
+ si_query_buffer_destroy(sctx->screen, &query->buffer);
FREE(query);
}
si_query_buffer_reset(ctx, &query->buffer);
- LIST_ADDTAIL(&query->b.active_list, &ctx->active_queries);
+ list_addtail(&query->b.active_list, &ctx->active_queries);
ctx->num_cs_dw_queries_suspend += query->b.num_cs_dw_suspend;
si_pc_query_resume(ctx, squery);
return (struct pipe_query *)query;
error:
- si_pc_query_destroy(screen, &query->b);
+ si_pc_query_destroy((struct si_context *)ctx, &query->b);
return NULL;
}
unsigned i;
switch (screen->info.chip_class) {
- case CIK:
+ case GFX7:
blocks = groups_CIK;
num_blocks = ARRAY_SIZE(groups_CIK);
break;
- case VI:
+ case GFX8:
blocks = groups_VI;
num_blocks = ARRAY_SIZE(groups_VI);
break;
blocks = groups_gfx9;
num_blocks = ARRAY_SIZE(groups_gfx9);
break;
- case SI:
+ case GFX6:
default:
return; /* not implemented */
}
if (screen->info.max_sh_per_se != 1) {
- /* This should not happen on non-SI chips. */
+ /* This should not happen on non-GFX6 chips. */
fprintf(stderr, "si_init_perfcounters: max_sh_per_se = %d not "
"supported (inaccurate performance counters)\n",
screen->info.max_sh_per_se);
for (i = 0; i < num_blocks; ++i) {
struct si_pc_block *block = &pc->blocks[i];
block->b = &blocks[i];
- block->num_instances = block->b->instances;
+ block->num_instances = MAX2(1, block->b->instances);
if (!strcmp(block->b->b->name, "CB") ||
!strcmp(block->b->b->name, "DB"))