radeonsi: implement ARB_shader_group_vote

[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index d04abb6d2038dd5212635aff31ae2e6ae610900a..8aae11d3be457ad914576e2b256e95e979ec8a02 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -416,12 +416,17 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
        case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
        case PIPE_CAP_DOUBLES:
+       case PIPE_CAP_TGSI_TEX_TXF_LZ:
                return 1;
 
        case PIPE_CAP_INT64:
        case PIPE_CAP_INT64_DIVMOD:
+       case PIPE_CAP_TGSI_CLOCK:
                return HAVE_LLVM >= 0x0309;
 
+       case PIPE_CAP_TGSI_VOTE:
+               return HAVE_LLVM >= 0x0400;
+
        case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
                return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 
@@ -451,6 +456,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return HAVE_LLVM >= 0x0309 ? 4 : 0;
 
        case PIPE_CAP_GLSL_FEATURE_LEVEL:
+               if (sscreen->b.chip_class >= GFX9)
+                       return 140;
                if (si_have_tgsi_compute(sscreen))
                        return 450;
                return HAVE_LLVM >= 0x0309 ? 420 : 410;
@@ -476,7 +483,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
        case PIPE_CAP_VERTEXID_NOBASE:
        case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
-       case PIPE_CAP_TGSI_VOTE:
        case PIPE_CAP_MAX_WINDOW_RECTANGLES:
        case PIPE_CAP_NATIVE_FENCE_FD:
        case PIPE_CAP_TGSI_FS_FBFETCH:
@@ -496,7 +502,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return 30;
 
        case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
-               return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
+               return sscreen->b.chip_class <= VI ?
+                       PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 
        /* Stream output. */
        case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
@@ -564,7 +571,9 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        return 0;
 }
 
-static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
+static int si_get_shader_param(struct pipe_screen* pscreen,
+                              enum pipe_shader_type shader,
+                              enum pipe_shader_cap param)
 {
        struct si_screen *sscreen = (struct si_screen *)pscreen;
 
@@ -572,9 +581,12 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
        {
        case PIPE_SHADER_FRAGMENT:
        case PIPE_SHADER_VERTEX:
+               break;
        case PIPE_SHADER_GEOMETRY:
        case PIPE_SHADER_TESS_CTRL:
        case PIPE_SHADER_TESS_EVAL:
+               if (sscreen->b.chip_class >= GFX9)
+                       return 0;
                break;
        case PIPE_SHADER_COMPUTE:
                switch (param) {
@@ -681,14 +693,10 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
        };
        unsigned i;
 
-       if (!sscreen)
-               return;
-
        if (!sscreen->b.ws->unref(sscreen->b.ws))
                return;
 
-       if (util_queue_is_initialized(&sscreen->shader_compiler_queue))
-               util_queue_destroy(&sscreen->shader_compiler_queue);
+       util_queue_destroy(&sscreen->shader_compiler_queue);
 
        for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
                if (sscreen->tm[i])
@@ -704,7 +712,7 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
                        FREE(part);
                }
        }
-       pipe_mutex_destroy(sscreen->shader_parts_mutex);
+       mtx_destroy(&sscreen->shader_parts_mutex);
        si_destroy_shader_cache(sscreen);
        r600_destroy_common_screen(&sscreen->b);
 }
@@ -732,6 +740,7 @@ static bool si_init_gs_info(struct si_screen *sscreen)
        case CHIP_POLARIS10:
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
+       case CHIP_VEGA10:
                sscreen->gs_table_depth = 32;
                return true;
        default:
@@ -752,7 +761,9 @@ static void si_handle_env_var_force_family(struct si_screen *sscreen)
                        /* Override family and chip_class. */
                        sscreen->b.family = sscreen->b.info.family = i;
 
-                       if (i >= CHIP_TONGA)
+                       if (i >= CHIP_VEGA10)
+                               sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
+                       else if (i >= CHIP_TONGA)
                                sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
                        else if (i >= CHIP_BONAIRE)
                                sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
@@ -794,6 +805,17 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
                return NULL;
        }
 
+       /* Only enable as many threads as we have target machines and CPUs. */
+       num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
+       num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
+
+       if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
+                            32, num_compiler_threads)) {
+               si_destroy_shader_cache(sscreen);
+               FREE(sscreen);
+               return NULL;
+       }
+
        si_handle_env_var_force_family(sscreen);
 
        if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
@@ -826,7 +848,20 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 
        sscreen->b.has_cp_dma = true;
        sscreen->b.has_streamout = true;
-       pipe_mutex_init(sscreen->shader_parts_mutex);
+
+       /* Some chips have RB+ registers, but don't support RB+. Those must
+        * always disable it.
+        */
+       if (sscreen->b.family == CHIP_STONEY ||
+           sscreen->b.chip_class >= GFX9) {
+               sscreen->b.has_rbplus = true;
+
+               sscreen->b.rbplus_allowed =
+                       !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
+                       sscreen->b.family == CHIP_STONEY;
+       }
+
+       (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
        sscreen->use_monolithic_shaders =
                (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 
@@ -838,16 +873,9 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
        if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
                sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 
-       /* Only enable as many threads as we have target machines and CPUs. */
-       num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
-       num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
-
        for (i = 0; i < num_compiler_threads; i++)
                sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
 
-       util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
-                        32, num_compiler_threads);
-
        /* Create the auxiliary context. This must be done last. */
        sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);