static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
{
- switch (ctx->type) {
- case PIPE_SHADER_TESS_CTRL:
+ switch (ctx->stage) {
+ case MESA_SHADER_TESS_CTRL:
return si_unpack_param(ctx, ctx->args.tcs_rel_ids, 0, 8);
- case PIPE_SHADER_TESS_EVAL:
+ case MESA_SHADER_TESS_EVAL:
return ac_get_arg(&ctx->ac, ctx->tes_rel_patch_id);
default:
static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
{
- assert(ctx->type == PIPE_SHADER_TESS_CTRL);
+ assert(ctx->stage == MESA_SHADER_TESS_CTRL);
if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 0, 13);
const struct si_shader_info *info = &ctx->shader->selector->info;
- unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
+ unsigned tcs_out_vertices = info->base.tess.tcs_vertices_out;
unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride + num_patch_outputs * 4;
static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
{
unsigned tcs_out_vertices =
- ctx->shader->selector ? ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT]
+ ctx->shader->selector ? ctx->shader->selector->info.base.tess.tcs_vertices_out
: 0;
/* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
- if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
+ if (ctx->stage == MESA_SHADER_TESS_CTRL && tcs_out_vertices)
return LLVMConstInt(ctx->ac.i32, tcs_out_vertices, 0);
return si_unpack_param(ctx, ctx->tcs_offchip_layout, 6, 6);
{
unsigned stride;
- switch (ctx->type) {
- case PIPE_SHADER_VERTEX:
+ switch (ctx->stage) {
+ case MESA_SHADER_VERTEX:
stride = ctx->shader->selector->lshs_vertex_stride / 4;
return LLVMConstInt(ctx->ac.i32, stride, 0);
- case PIPE_SHADER_TESS_CTRL:
+ case MESA_SHADER_TESS_CTRL:
if (ctx->screen->info.chip_class >= GFX9 && ctx->shader->is_monolithic) {
stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
return LLVMConstInt(ctx->ac.i32, stride, 0);
static LLVMValueRef
get_dw_address_from_generic_indices(struct si_shader_context *ctx, LLVMValueRef vertex_dw_stride,
LLVMValueRef base_addr, LLVMValueRef vertex_index,
- LLVMValueRef param_index, ubyte name, ubyte index)
+ LLVMValueRef param_index, ubyte name)
{
if (vertex_dw_stride) {
base_addr = ac_build_imad(&ctx->ac, vertex_index, vertex_dw_stride, base_addr);
base_addr = ac_build_imad(&ctx->ac, param_index, LLVMConstInt(ctx->ac.i32, 4, 0), base_addr);
}
- int param = name == TGSI_SEMANTIC_PATCH || name == TGSI_SEMANTIC_TESSINNER ||
- name == TGSI_SEMANTIC_TESSOUTER
- ? si_shader_io_get_unique_index_patch(name, index)
- : si_shader_io_get_unique_index(name, index, false);
+ int param = name >= VARYING_SLOT_PATCH0 ||
+ name == VARYING_SLOT_TESS_LEVEL_INNER ||
+ name == VARYING_SLOT_TESS_LEVEL_OUTER
+ ? si_shader_io_get_unique_index_patch(name)
+ : si_shader_io_get_unique_index(name, false);
/* Add the base address of the element. */
return LLVMBuildAdd(ctx->ac.builder, base_addr, LLVMConstInt(ctx->ac.i32, param * 4, 0), "");
static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(struct si_shader_context *ctx,
LLVMValueRef vertex_index,
LLVMValueRef param_index,
- ubyte name, ubyte index)
+ ubyte name)
{
unsigned param_index_base;
- param_index_base = name == TGSI_SEMANTIC_PATCH || name == TGSI_SEMANTIC_TESSINNER ||
- name == TGSI_SEMANTIC_TESSOUTER
- ? si_shader_io_get_unique_index_patch(name, index)
- : si_shader_io_get_unique_index(name, index, false);
+ param_index_base = name >= VARYING_SLOT_PATCH0 ||
+ name == VARYING_SLOT_TESS_LEVEL_INNER ||
+ name == VARYING_SLOT_TESS_LEVEL_OUTER
+ ? si_shader_io_get_unique_index_patch(name)
+ : si_shader_io_get_unique_index(name, false);
if (param_index) {
param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct si_shader_info *info = &ctx->shader->selector->info;
LLVMValueRef dw_addr, stride;
- ubyte name, index;
+ ubyte semantic;
driver_location = driver_location / 4;
if (load_input) {
- name = info->input_semantic_name[driver_location];
- index = info->input_semantic_index[driver_location];
+ semantic = info->input_semantic[driver_location];
} else {
- name = info->output_semantic_name[driver_location];
- index = info->output_semantic_index[driver_location];
+ semantic = info->output_semantic[driver_location];
}
bool is_patch = vertex_index == NULL;
- assert((name == TGSI_SEMANTIC_PATCH || name == TGSI_SEMANTIC_TESSINNER ||
- name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
+ assert((semantic >= VARYING_SLOT_PATCH0 ||
+ semantic == VARYING_SLOT_TESS_LEVEL_INNER ||
+ semantic == VARYING_SLOT_TESS_LEVEL_OUTER) == is_patch);
if (load_input) {
stride = get_tcs_in_vertex_dw_stride(ctx);
}
dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr, vertex_index, param_index,
- name, index);
+ semantic);
LLVMValueRef value[4];
for (unsigned i = 0; i < num_components; i++) {
LLVMValueRef base, addr;
driver_location = driver_location / 4;
- ubyte name = info->input_semantic_name[driver_location];
- ubyte index = info->input_semantic_index[driver_location];
+ ubyte semantic = info->input_semantic[driver_location];
- assert((name == TGSI_SEMANTIC_PATCH || name == TGSI_SEMANTIC_TESSINNER ||
- name == TGSI_SEMANTIC_TESSOUTER) == (vertex_index == NULL));
+ assert((semantic >= VARYING_SLOT_PATCH0 ||
+ semantic == VARYING_SLOT_TESS_LEVEL_INNER ||
+ semantic == VARYING_SLOT_TESS_LEVEL_OUTER) == (vertex_index == NULL));
base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
}
addr =
- get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index, param_index, name, index);
+ get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index, param_index, semantic);
/* TODO: This will generate rather ordinary llvm code, although it
* should be easy for the optimiser to fix up. In future we might want
if (ac_get_type_size(type) == 8) {
offset *= 2;
if (offset == 4) {
- ubyte name = info->input_semantic_name[driver_location + 1];
- ubyte index = info->input_semantic_index[driver_location + 1];
+ ubyte semantic = info->input_semantic[driver_location + 1];
addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index, param_index,
- name, index);
+ semantic);
}
offset = offset % 4;
bool is_tess_factor = false, is_tess_inner = false;
driver_location = driver_location / 4;
- ubyte name = info->output_semantic_name[driver_location];
- ubyte index = info->output_semantic_index[driver_location];
+ ubyte semantic = info->output_semantic[driver_location];
bool is_const = !param_index;
if (!param_index)
const bool is_patch = vertex_index == NULL;
/* Invalid SPIR-V can cause this. */
- if ((name == TGSI_SEMANTIC_PATCH || name == TGSI_SEMANTIC_TESSINNER ||
- name == TGSI_SEMANTIC_TESSOUTER) != is_patch)
+ if ((semantic >= VARYING_SLOT_PATCH0 || semantic == VARYING_SLOT_TESS_LEVEL_INNER ||
+ semantic == VARYING_SLOT_TESS_LEVEL_OUTER) != is_patch)
return;
if (!is_patch) {
stride = get_tcs_out_vertex_dw_stride(ctx);
dw_addr = get_tcs_out_current_patch_offset(ctx);
dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr, vertex_index, param_index,
- name, index);
+ semantic);
} else {
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr, vertex_index, param_index,
- name, index);
+ semantic);
if (is_const && const_index == 0) {
- int name = info->output_semantic_name[driver_location];
+ int semantic = info->output_semantic[driver_location];
/* Always write tess factors into LDS for the TCS epilog. */
- if (name == TGSI_SEMANTIC_TESSINNER || name == TGSI_SEMANTIC_TESSOUTER) {
+ if (semantic == VARYING_SLOT_TESS_LEVEL_INNER ||
+ semantic == VARYING_SLOT_TESS_LEVEL_OUTER) {
is_tess_factor = true;
- is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
+ is_tess_inner = semantic == VARYING_SLOT_TESS_LEVEL_INNER;
}
}
}
base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
addr =
- get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index, param_index, name, index);
+ get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index, param_index, semantic);
for (unsigned chan = component; chan < 8; chan++) {
if (!(writemask & (1 << chan)))
unsigned buffer_store_offset = chan % 4;
if (chan == 4) {
- ubyte name = info->output_semantic_name[driver_location + 1];
- ubyte index = info->output_semantic_index[driver_location + 1];
+ ubyte semantic = info->output_semantic[driver_location + 1];
addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index, param_index,
- name, index);
+ semantic);
}
/* Skip LDS stores if there is no LDS read of this output. */
ctx->ac.f32_0, ctx->ac.f32_0};
/* For triangles, the vector should be (u, v, 1-u-v). */
- if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_TRIANGLES) {
+ if (ctx->shader->selector->info.base.tess.primitive_mode == GL_TRIANGLES) {
coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
}
return ac_build_gather_values(&ctx->ac, coord, 4);
}
-static LLVMValueRef load_tess_level(struct si_shader_context *ctx, unsigned semantic_name)
+static LLVMValueRef load_tess_level(struct si_shader_context *ctx, unsigned semantic)
{
LLVMValueRef base, addr;
- int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
+ int param = si_shader_io_get_unique_index_patch(semantic);
base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
return buffer_load(ctx, ctx->ac.f32, ~0, ctx->tess_offchip_ring, base, addr, true);
}
-static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx, unsigned semantic_name)
+static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx, unsigned sysval)
{
LLVMValueRef buf, slot, val[4];
int i, offset;
slot = LLVMConstInt(ctx->ac.i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
buf = ac_get_arg(&ctx->ac, ctx->rw_buffers);
buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
- offset = semantic_name == TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL ? 4 : 0;
+ offset = sysval == SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT ? 4 : 0;
for (i = 0; i < 4; i++)
val[i] = si_buffer_load_const(ctx, buf, LLVMConstInt(ctx->ac.i32, (offset + i) * 4, 0));
bool load_default_state)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
- unsigned semantic_name;
+ unsigned semantic;
if (load_default_state) {
switch (varying_id) {
case VARYING_SLOT_TESS_LEVEL_INNER:
- semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL;
+ semantic = SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT;
break;
case VARYING_SLOT_TESS_LEVEL_OUTER:
- semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL;
+ semantic = SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT;
break;
default:
unreachable("unknown tess level");
}
- return load_tess_level_default(ctx, semantic_name);
+ return load_tess_level_default(ctx, semantic);
}
switch (varying_id) {
case VARYING_SLOT_TESS_LEVEL_INNER:
- semantic_name = TGSI_SEMANTIC_TESSINNER;
+ semantic = VARYING_SLOT_TESS_LEVEL_INNER;
break;
case VARYING_SLOT_TESS_LEVEL_OUTER:
- semantic_name = TGSI_SEMANTIC_TESSOUTER;
+ semantic = VARYING_SLOT_TESS_LEVEL_OUTER;
break;
default:
unreachable("unknown tess level");
}
- return load_tess_level(ctx, semantic_name);
+ return load_tess_level(ctx, semantic);
}
static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
- if (ctx->type == PIPE_SHADER_TESS_CTRL)
+ if (ctx->stage == MESA_SHADER_TESS_CTRL)
return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 13, 6);
- else if (ctx->type == PIPE_SHADER_TESS_EVAL)
+ else if (ctx->stage == MESA_SHADER_TESS_EVAL)
return get_num_tcs_out_vertices(ctx);
else
- unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
+ unreachable("invalid shader stage for VERTICESIN");
}
/**
/* Determine the layout of one tess factor element in the buffer. */
switch (shader->key.part.tcs.epilog.prim_mode) {
- case PIPE_PRIM_LINES:
+ case GL_LINES:
stride = 2; /* 2 dwords, 1 vec2 store */
outer_comps = 2;
inner_comps = 0;
break;
- case PIPE_PRIM_TRIANGLES:
+ case GL_TRIANGLES:
stride = 4; /* 4 dwords, 1 vec4 store */
outer_comps = 3;
inner_comps = 1;
break;
- case PIPE_PRIM_QUADS:
+ case GL_QUADS:
stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
outer_comps = 4;
inner_comps = 2;
/* Load tess_inner and tess_outer from LDS.
* Any invocation can write them, so we can't get them from a temporary.
*/
- tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
- tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
+ tess_inner_index = si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER);
+ tess_outer_index = si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_OUTER);
lds_base = tcs_out_current_patch_data_offset;
lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
}
}
- if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
+ if (shader->key.part.tcs.epilog.prim_mode == GL_LINES) {
/* For isolines, the hardware expects tess factors in the
* reverse order from what NIR specifies.
*/
buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
- param_outer = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
+ param_outer = si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_OUTER);
tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
LLVMConstInt(ctx->ac.i32, param_outer, 0));
ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec, outer_comps, tf_outer_offset, base, 0,
ac_glc);
if (inner_comps) {
- param_inner = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
+ param_inner = si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER);
tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
LLVMConstInt(ctx->ac.i32, param_inner, 0));
/* Write outputs to LDS. The next shader (TCS aka HS) will read
* its inputs from it. */
for (i = 0; i < info->num_outputs; i++) {
- unsigned name = info->output_semantic_name[i];
- unsigned index = info->output_semantic_index[i];
+ unsigned semantic = info->output_semantic[i];
/* The ARB_shader_viewport_layer_array spec contains the
* following issue:
*
* So writes to those outputs in VS-as-LS are simply ignored.
*/
- if (name == TGSI_SEMANTIC_LAYER || name == TGSI_SEMANTIC_VIEWPORT_INDEX)
+ if (semantic == VARYING_SLOT_LAYER || semantic == VARYING_SLOT_VIEWPORT)
continue;
- int param = si_shader_io_get_unique_index(name, index, false);
+ int param = si_shader_io_get_unique_index(semantic, false);
LLVMValueRef dw_addr =
LLVMBuildAdd(ctx->ac.builder, base_dw_addr, LLVMConstInt(ctx->ac.i32, param * 4, 0), "");
projects / mesa.git / blobdiff