break;
case nir_intrinsic_bindless_image_store:
info->uses_bindless_images = true;
- info->writes_memory = true;
info->num_memory_stores++;
break;
case nir_intrinsic_image_deref_store:
- info->writes_memory = true;
info->num_memory_stores++;
break;
case nir_intrinsic_bindless_image_atomic_add:
case nir_intrinsic_bindless_image_atomic_exchange:
case nir_intrinsic_bindless_image_atomic_comp_swap:
info->uses_bindless_images = true;
- info->writes_memory = true;
info->num_memory_stores++;
break;
case nir_intrinsic_image_deref_atomic_add:
case nir_intrinsic_image_deref_atomic_comp_swap:
case nir_intrinsic_image_deref_atomic_inc_wrap:
case nir_intrinsic_image_deref_atomic_dec_wrap:
- info->writes_memory = true;
info->num_memory_stores++;
break;
case nir_intrinsic_store_ssbo:
case nir_intrinsic_ssbo_atomic_xor:
case nir_intrinsic_ssbo_atomic_exchange:
case nir_intrinsic_ssbo_atomic_comp_swap:
- info->writes_memory = true;
info->num_memory_stores++;
break;
case nir_intrinsic_load_color0: