radeonsi: stop using TGSI_PROPERTY_CS_*
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
index 3bbba5eacf4b7520a35ac5aaf4341b79a35825ec..ae859430291b7837e9dc5b8afc7b484a340ceec8 100644 (file)
@@ -289,7 +289,7 @@ static void scan_instruction(const struct nir_shader *nir, struct si_shader_info
          break;
       case nir_intrinsic_load_local_group_size:
          /* The block size is translated to IMM with a fixed block size. */
-         if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
+         if (info->base.cs.local_size[0] == 0)
             info->uses_block_size = true;
          break;
       case nir_intrinsic_load_local_invocation_id:
@@ -504,14 +504,6 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
                                                                       TGSI_INTERPOLATE_LOC_CENTER;
    }
 
-   if (gl_shader_stage_is_compute(nir->info.stage)) {
-      info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
-      info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
-      info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
-      info->properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD] =
-         nir->info.cs.user_data_components_amd;
-   }
-
    info->constbuf0_num_slots = nir->num_uniforms;
    info->shader_buffers_declared = u_bit_consecutive(0, nir->info.num_ssbos);
    info->const_buffers_declared = u_bit_consecutive(0, nir->info.num_ubos);