amd/common,radeonsi: Move gfx10_format_table to common.

[mesa.git] / src / gallium / drivers / radeonsi / si_state.c

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 19fb5a9cd1b2933eef72ddf1861817f78ac88b7b..470542354eb3131fc9842ee573c55fa906181857 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -42,7 +42,7 @@ struct gfx10_format {
    bool buffers_only : 1;
 };
 
-#include "gfx10_format_table.h"
+#include "amd/common/gfx10_format_table.h"
 
 static unsigned si_map_swizzle(unsigned swizzle)
 {
@@ -2830,7 +2830,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
       else
          sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
 
-      if (tex->surface.dcc_offset)
+      if (tex->surface.display_dcc_offset)
          sctx->framebuffer.displayable_dcc_cb_mask |= 1 << i;
 
       /* Don't update nr_color_samples for non-AA buffers.
@@ -3810,7 +3810,7 @@ static void gfx10_make_texture_descriptor(
    state[6] = 0;
    state[7] = 0;
 
-   if (tex->surface.dcc_offset) {
+   if (vi_dcc_enabled(tex, first_level)) {
       state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
                   S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.dcc.max_compressed_block_size) |
                   S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
@@ -4071,7 +4071,7 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu
       state[5] |= S_008F24_LAST_ARRAY(last_layer);
    }
 
-   if (tex->surface.dcc_offset) {
+   if (vi_dcc_enabled(tex, first_level)) {
       state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
    } else {
       /* The last dword is unused by hw. The shader uses it to clear
@@ -4479,7 +4479,8 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
    unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso : state->max_anisotropy;
    unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
    bool trunc_coord = state->min_img_filter == PIPE_TEX_FILTER_NEAREST &&
-                      state->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
+                      state->mag_img_filter == PIPE_TEX_FILTER_NEAREST &&
+                      state->compare_mode == PIPE_TEX_COMPARE_NONE;
    union pipe_color_union clamped_border_color;
 
    if (!rstate) {
@@ -5155,8 +5156,8 @@ static void si_init_config(struct si_context *sctx)
       return;
 
    si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
-   si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
-   si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
+   si_pm4_cmd_add(pm4, CC0_UPDATE_LOAD_ENABLES(1));
+   si_pm4_cmd_add(pm4, CC1_UPDATE_SHADOW_ENABLES(1));
    si_pm4_cmd_end(pm4, false);
 
    if (has_clear_state) {
@@ -5269,8 +5270,8 @@ static void si_init_config(struct si_context *sctx)
       }
 
       /* Compute LATE_ALLOC_VS.LIMIT. */
-      unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
-      unsigned late_alloc_wave64 = 0; /* The limit is per SH. */
+      unsigned num_cu_per_sh = sscreen->info.min_good_cu_per_sa;
+      unsigned late_alloc_wave64 = 0; /* The limit is per SA. */
       unsigned cu_mask_vs = 0xffff;
       unsigned cu_mask_gs = 0xffff;
 
@@ -5294,7 +5295,7 @@ static void si_init_config(struct si_context *sctx)
          if (!sscreen->info.use_late_alloc) {
             late_alloc_wave64 = 0;
          } else if (num_cu_per_sh <= 4) {
-            /* Too few available compute units per SH. Disallowing
+            /* Too few available compute units per SA. Disallowing
              * VS to run on one CU could hurt us more than late VS
              * allocation would help.
              *
@@ -5415,6 +5416,5 @@ static void si_init_config(struct si_context *sctx)
       si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
    }
 
-   si_pm4_upload_indirect_buffer(sctx, pm4);
    sctx->init_config = pm4;
 }